plxv

Prefixed Load VSX Vector 8LS:D-form

plxv RT,RA,RB

Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.

Details

The plxv instruction is a prefixed load that loads a 128-bit VSX vector from a memory location into a VSX target register. It uses the 8LS:D-form encoding, which combines a prefix word with a suffix word to provide an extended displacement field. The effective address is computed by adding the (possibly sign-extended) displacement to the contents of register RA, or to 0 if RA=0. This instruction was introduced in PowerISA v3.1 and is part of the VSX facility.

Pseudocode Operation

Not available in specification

Programming Note

The plxv instruction is used for loading a 128-bit VSX vector from memory into a target register, using an extended displacement field provided by the prefix word. Ensure that the base address register (RA) contains the correct pointer or is zero if no base address is needed. This instruction requires the VSX facility and is available in PowerISA v3.1 and later.

Example

plxv r3, r4, r5

Encoding

Binary Layout
000001
0
000
6
Rc
9
.//..
10
RT
11
RA
16
RB
21
 
Format D-form
Opcode 0x00000000
Extension Prefixed

Operands

  • RT
    Target General Purpose Register
  • RA
    Source General Purpose Register
  • RB
    Source General Purpose Register