plxv

Prefixed Load VSX Vector 8LS:D-form

plxv RT,RA,RB

Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.

Encoding

Binary Layout

000001

0:5

000

6:8

Rc

9

.//..

10

RT

11:15

RA

16:20

RB

21:63

 

Format D-form

Opcode 0x04000000C8000000

Extension Prefixed

Operands

• RT
  Target General Purpose Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

plxv r3, r4, r5

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 128-bit VSX vector from memory into VSX register RT using a prefixed instruction with a 34-bit signed displacement. The address is computed as RA + displacement (scaled by 4). This is a VSX instruction requiring the VSX category and the Prefixed instruction set.

Operation

EA ← (RA) + (DQ || Disp)
RT ← MEM(EA, 16)

Programming Note

The plxv instruction is used for loading a 128-bit VSX vector from memory into a target register, using an extended displacement field provided by the prefix word. Ensure that the base address register (RA) contains the correct pointer or is zero if no base address is needed. This instruction requires the VSX facility and is available in PowerISA v3.1 and later.