vmulosh

Vector Multiply Odd Signed Halfword

vmulosh vD, vA, vB

Multiplies odd signed halfwords to words.

Details

Multiplies the odd-indexed signed halfwords from vA and vB, producing signed word results in vD. Operates on halfwords at indices 1 and 3, generating two word products. No condition flags are affected.

Pseudocode Operation

vD[0:31] ← (vA[16:31] × vB[16:31]) as signed
vD[32:63] ← (vA[48:63] × vB[48:63]) as signed
vD[64:95] ← (vA[80:95] × vB[80:95]) as signed
vD[96:127] ← (vA[112:127] × vB[112:127]) as signed

Programming Note

This instruction is useful for performing element-wise multiplication of odd-numbered signed halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored as 32-bit words in the destination vector, so ensure proper alignment and size of the vectors to avoid unexpected behavior.

Example

vmulosh vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
328
21
 
Format VX-form
Opcode 0x10000148
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B