vminsh

Vector Minimum Signed Halfword

vminsh vD, vA, vB

Compares the signed halfwords of two vector registers and selects the minimum value for each corresponding pair.

Details

For vminsh, the instruction compares the signed halfwords of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding halfword element of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ← VSR[VRA+32].hword[i]
    src2 ← VSR[VRB+32].hword[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].hword[i] ← lt_flag=1 ? src1 : src2
end

Programming Note

This instruction is used to perform element-wise minimum comparison of signed halfwords from two vector registers and store the results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords, so negative values are correctly handled. There are no specific alignment requirements for the data being processed.

Example

vminsh vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1602
 
Format VA-form
Opcode 0x10000642
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register