xsmsubadp

VSX Scalar Multiply-Subtract Type-A Double-Precision

xsmsubadp XT,XA,XB

Performs a double-precision floating-point multiply-subtract operation.

Encoding

Binary Layout

Format XX3-form

Opcode 0xF0000188

Extension VSX

Operands

XT
Target Vector-Scalar Register
XA
Source Vector-Scalar Register
XB
Source Vector-Scalar Register

Example

xsmsubadp vs1, vs2, vs3

Registers Altered

FPSCR, VSR[XT]

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xsmsubadp, the value in VSR[XA] is multiplied by the value in VSR[XT], and then the result is subtracted from the value in VSR[XB].

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[32×TX+T].dword[0] ←result
  VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
  FPSCR.FPRF ←fprf_CLASS_BFP64(result)
  FPSCR.FR ←inc_flag
  FPSCR.FI ←xx_flag
end else do
  FPSCR.FI ←0b0
end

Programming Note

This instruction is commonly used for performing complex floating-point arithmetic operations involving multiplication and subtraction. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow or underflow conditions, as indicated by the FPSCR flags. The operation requires proper alignment of the input values, specifically 64-bit double-precision floating-point numbers.