plh

Prefixed Load Halfword

plh RT, D(RA), R

Loads 16-bit halfword using 34-bit offset.

Details

Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix) and zero-extends the loaded value into the target register. The effective address is computed from a base register or the program counter (determined by the R bit), and both absolute and PC-relative modes are supported. This is a two-instruction prefixed load with no condition register or status flag effects.

Pseudocode Operation

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← (0)^48 || MEM(EA, 2)

Example

plh r3, 0(r4), 0

Encoding

Binary Layout
1
0
2
6
R
8
0
9
D0
14
40
32
RT
38
RA
43
D1
48
 
Format MLS:D-form
Opcode 0x04000000A0000000
Extension Prefixed

Operands

  • RT
    Target
  • D
    Offset
  • RA
    Base
  • R
    PC-Rel