plh

Prefixed Load Halfword

plh RT, D(RA), R

Loads 16-bit halfword using 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

40

32:37

RT

38:42

RA

43:47

D1

48:63

 

Format MLS:D-form

Opcode 0x04000000A0000000

Extension Prefixed

Operands

• RT
  Target
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

plh r3, 0(r4), 0

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix) and zero-extends the loaded value into the target register. The effective address is computed from a base register or the program counter (determined by the R bit), and both absolute and PC-relative modes are supported. This is a two-instruction prefixed load with no condition register or status flag effects.

Operation

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← (0)^48 || MEM(EA, 2)