xsaddqpo

VSX Scalar Add Quad-Precision Odd

xsaddqpo vD, vA, vB

Used for Quad-Precision arithmetic on hardware that splits quads.

Details

The xsaddqpo instruction performs a scalar addition of two quad-precision floating-point numbers, VRA and VRB, and places the result in VRT. The operation uses round-to-odd rounding mode.

Pseudocode Operation

src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_ADD(src1, src2)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE &

Programming Note

The xsaddqpo instruction is used for adding two quad-precision floating-point numbers using the round-to-odd rounding mode. Ensure that the input operands are correctly aligned and that the VSX registers are properly set up. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if invalid operations occur, such as signaling NaNs or infinities. Performance can be impacted by the precision of the operation and the current rounding mode settings in the FPSCR register.

Example

xsaddqpo vd, va, vb

Encoding

Binary Layout
63
0
vD
6
vA
11
vB
16
4
21
/
31
 
Format X-form
Opcode 0xFC000004
Extension VSX
Registers Altered FPSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B