veqv

Vector Logical Equivalence

veqv VRT,VRA,VRB

Performs a logical equivalence operation on the contents of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRA

11:15

VRB

16:20

1412

21:31

 

Format VX-form

Opcode 0x10000684

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

veqv v1, v2, v3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of VSR[VRA+32] are XORed with the contents of VSR[VRB+32] and the complemented result is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32] ← ¬(VSR[VRA+32] ≡ VSR[VRB+32])

Programming Note

The veqv instruction performs a logical equivalence operation between two vector registers, followed by a bitwise NOT on the result. This is useful for comparing vectors and determining where they differ. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised.