vpkswus

Vector Pack Signed Word Unsigned Saturate

vpkswus VRT,VSRA,VSRB

Packs signed words from two source vectors into one destination vector with unsigned saturation.

Encoding

Binary Layout

000100

0:5

VRT

6:10

VSRA

11:15

VSRB

16:20

00101

21:25

001110

26:31

 

Format VX-form

Opcode 0x1000014E

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VSRA
  Source Vector Register A
• VSRB
  Source Vector Register B

Example

vpkswus v1, vs2, vs3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Packs signed 32-bit word elements from vectors VSRA and VSRB into 16-bit unsigned elements in VRT, saturating to the unsigned 16-bit range [0, 65535] if any source element overflows. The operation interleaves words from VSRA and VSRB into the result. This instruction requires VMX/AltiVec support and no condition registers are modified.

Operation

for i in 0..3:
  VRT[i*16 : i*16+15] ← saturate_unsigned_16bit(VSRA[i*32 : i*32+31])
  VRT[(i+4)*16 : (i+4)*16+15] ← saturate_unsigned_16bit(VSRB[i*32 : i*32+31])

Programming Note

The vpkswus instruction is useful for efficiently packing and converting signed 32-bit integers to unsigned 16-bit integers with saturation. Ensure that the input vectors are correctly aligned and that the operation does not exceed the bounds of the target vector register. This instruction operates at user privilege level and will raise an exception if any invalid operand access occurs.