vpkswus
Vector Pack Signed Word Unsigned Saturate
Packs signed words from two source vectors into one destination vector with unsigned saturation.
Details
The vpkswus instruction packs four signed 32-bit integer elements from vector register VSRA and four signed 32-bit integer elements from vector register VSRB into eight 16-bit unsigned integer elements stored in vector register VRT. Each signed word element is saturated to an unsigned halfword range (0x0000 to 0xFFFF); if the source value is negative it saturates to 0, and if it exceeds 0xFFFF it saturates to 0xFFFF. The eight elements from VSRA occupy the upper half of VRT and the eight elements from VSRB occupy the lower half.
Programming Note
The vpkswus instruction is useful for efficiently packing and converting signed 32-bit integers to unsigned 16-bit integers with saturation. Ensure that the input vectors are correctly aligned and that the operation does not exceed the bounds of the target vector register. This instruction operates at user privilege level and will raise an exception if any invalid operand access occurs.
Example
Encoding
Operands
-
VRT
Target Vector Register -
VSRA
Source Vector Register A -
VSRB
Source Vector Register B