vsraw

Vector Shift Right Algebraic Word

vsraw vD, vA, vB

Shifts each word element of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

900

21:31

Format VX-form

Opcode 0x10000384

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Shift Count Vector Register

Example

vsraw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsraw, each word element of VSR[VRA+32] is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32]. The result is placed into the corresponding word element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← CHOP32(EXTS(src1) >> src2)
end

Programming Note

The vsraw instruction performs a right algebraic shift on each word element of the source vector, using the low-order 5 bits of the corresponding element in the second source vector as the shift count. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment; while vsraw does not require specific alignment, incorrect alignment can lead to performance penalties or exceptions if data is not properly aligned in memory.