vrlh

Vector Rotate Left Halfword

vrlh vD, vA, vB

Rotates each halfword left.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

68

21:31

 

Format VX-form

Opcode 0x10000044

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Data
• vB
  Rotate Count

Example

vrlh vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rotates each of the eight 16-bit elements in vA left by the number of bits specified by the corresponding 16-bit element in vB. The rotate count is masked to bits 0-3 (modulo 16). No condition register or status flags are affected.

Operation

for i in 0 to 7 do
  shift_amount ← vB[i*16+0:i*16+15] & 0xF
  vD[i*16+0:i*16+15] ← ROTL16(vA[i*16+0:i*16+15], shift_amount)

Programming Note

The vrlh instruction is commonly used for bit manipulation tasks that require rotating halfwords within a vector. Ensure that the source and destination vectors are properly aligned to avoid data corruption. This instruction operates at user privilege level, but if MSR.VEC is not set, it will raise a Vector_Unavailable exception. Performance may vary based on the specific implementation and the alignment of the input vectors.