xvf64ger

VSX Vector Float64 GER (Rank-1 Update)

xvf64ger AT, XA, XB

Performs a vector floating-point general element-wise reduction on 64-bit elements.

Encoding

Binary Layout

59

0:5

AT

6:8

//

9:10

Ap

11:15

B

16:20

59

21:28

AX

29

BX

30

/

31

 

Format XX3-form

Opcode 0xEC0001D8

Extension MMA

Operands

• AT
  Accumulator
• XA
  Src A (FP64)
• XB
  Src B (FP64)
• XAp
  Source Vector Register

Example

xvf64ger acc0, vs2, vs3

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a rank-1 update of a 4×4 matrix accumulator using 64-bit floating-point elements from two VSX source registers. This MMA instruction computes the outer product of two vectors (each with 2 double-precision elements, implicitly extended) and accumulates the result into the 512-bit accumulator AT. No condition register or status flags are affected.

Operation

AT ← AT + (XA[0] * XB[0] || XA[0] * XB[1] || XA[1] * XB[0] || XA[1] * XB[1]) (as 4×4 FP64 matrix)

Programming Note

The xvf64ger instruction is commonly used for performing matrix operations in scientific computing and linear algebra. Ensure that the input vectors X and Y are properly aligned to avoid performance penalties. This instruction operates at user privilege level, but improper use can lead to undefined behavior if the accumulator register is not correctly initialized.