xvf64ger

VSX Vector Float64 GER (Rank-1 Update)

xvf64ger AT, XA, XB

Performs a vector floating-point general element-wise reduction on 64-bit elements.

Details

Performs a rank-1 update of a 4×4 matrix accumulator using 64-bit floating-point elements from two VSX source registers. This MMA instruction computes the outer product of two vectors (each with 2 double-precision elements, implicitly extended) and accumulates the result into the 512-bit accumulator AT. No condition register or status flags are affected.

Pseudocode Operation

AT ← AT + (XA[0] * XB[0] || XA[0] * XB[1] || XA[1] * XB[0] || XA[1] * XB[1]) (as 4×4 FP64 matrix)

Programming Note

The xvf64ger instruction is commonly used for performing matrix operations in scientific computing and linear algebra. Ensure that the input vectors X and Y are properly aligned to avoid performance penalties. This instruction operates at user privilege level, but improper use can lead to undefined behavior if the accumulator register is not correctly initialized.

Example

xvf64ger acc0, vs2, vs3

Encoding

Binary Layout
0
0
6
6
9
9
11
11
16
16
21
21
29
29
30
30
31
31
 
Format XX3-form
Opcode 0xF000003B
Extension MMA

Operands

  • AT
    Accumulator
  • XA
    Src A (FP64)
  • XB
    Src B (FP64)
  • XAp
    Source Vector Register