vmuluwm

Vector Multiply Unsigned Word Modulo

vmuluwm VRT,VRA,VRB

Multiplies the contents of two vector registers and places the low-order 32 bits of each product into a target vector register.

Details

For vmuluwm, each word element in VSR[VRA+32] is multiplied by the corresponding word element in VSR[VRB+32]. The low-order 32 bits of each product are placed into the corresponding word element in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(src1 × src2)
end

Programming Note

vmuluwm can be used for unsigned or signed integers.

Example

vmuluwm v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x10000089
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register