vdivsq

Vector Divide Signed Quadword

vdivsq VRT,VRA,VRB

Divides the contents of two vector registers and updates the destination register with the quotient.

Encoding

Binary Layout

VRT

VRA

VRB

Format VX-form

Opcode 0x1000010B

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vdivsq v1, v2, v3

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vdivsq, the signed integer value in VSR[VRA+32] is divided by the signed integer value in VSR[VRB+32], and the result is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()

dividend ← EXTS(VSR[VRA+32])
divisor ← EXTS(VSR[VRB+32])
VSR[VRT+32] ← CHOP128(dividend ÷ divisor)

Let src1 be the signed integer value in VSR[VRA+32].
Let src2 be the signed integer value in VSR[VRB+32].
The quotient of src1 divided by src2 is placed into VSR[VRT+32].
The quotient is the unique signed integer that satisfies dividend = (quotient × divisor) + r where 0 ≤ remainder < |divisor| if the dividend is nonnegative, and -|divisor| < remainder ≤ 0 if the dividend is negative.

If an attempt is made to perform any of the divisions <anything> ÷ 0 or 0x8000_0000_0000_0000_0000_0000_0000_0000 ÷ -1 then the contents of VSR[VRT+32] are undefined.

Programming Note

The vdivsq instruction performs a signed division of two 64-bit integers stored in vector registers. Ensure that the divisor is not zero to avoid undefined results. The operation requires the Vector Facility (MSR.VEC) to be enabled; otherwise, a Vector_Unavailable exception will occur. Be cautious with edge cases like dividing the smallest possible negative number by -1, which results in an undefined quotient.