vexpandqm

Vector Expand Quadword Mask

vexpandqm vD, vB

Expands bits from a GPR mask into a quadword-element vector.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1858

21:31

 

Format VX-form

Opcode 0x10040642

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vexpandqm vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Expands individual bits from a source vector register into quadword-sized elements in the destination vector register, where each bit controls whether the corresponding quadword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

Operation

for i in 0 to 1 do
  if vB[i] = 1 then
    vD[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
  else
    vD[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000
  end if
end for

Programming Note

The vexpandqm instruction is used to set all elements in a vector register based on the value of a single mask bit. Ensure that the Vector Facility (VEC) is enabled in the MSR before using this instruction; otherwise, it will raise an exception. This instruction is useful for quickly initializing vectors with either all ones or all zeros based on a condition.