vcmpneh.

Vector Compare Not Equal Halfword (Record)

vcmpneh. VRT,VRA,VRB

Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x10000047

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpneh v1, v2, v3

Registers Altered

CR6 (if Rc=1)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpneh, each halfword element in VSR[VRA+32] is compared with the corresponding element in VSR[VRB+32]. If they are not equal, the corresponding element in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←VSR[VRA+32].hword[i]
    src2 ←VSR[VRB+32].hword[i]
    if src1 != src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.