vcmpgefp

Vector Compare Greater Equal Floating-Point

vcmpgefp vD, vA, vB

Compares 4 floats (A >= B).

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

454

21:31

 

Format VC-form

Opcode 0x100001C6

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vcmpgefp vd, va, vb

Registers Altered

MSR, CR6

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares each of four 32-bit floating-point elements: vA >= vB. For each element, stores all 1s (0xFFFFFFFF) if the condition is true, or all 0s if false, into the corresponding word of vD. This instruction operates on VMX/AltiVec and does not modify the condition register.

Operation

for i in 0 to 3:
  if vA[32*i:32*i+31] >= vB[32*i:32*i+31] then
    vD[32*i:32*i+31] ← 0xFFFFFFFF
  else
    vD[32*i:32*i+31] ← 0x00000000

Programming Note

This instruction is commonly used for element-wise comparison of single-precision floating-point numbers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result of each comparison is stored as 0xFFFFFFFF if true or 0x0000_0000 if false in the target VSR. If Rc=1, CR Field 6 is updated to reflect whether all comparisons were true, all were false, or a mix of both.