vclzh

Vector Count Leading Zeros Halfword

vclzh vD, vB

Counts leading zeros in each halfword.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1858

21:31

 

Format VX-form

Opcode 0x10000742

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vclzh vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Counts the number of leading zero bits in each of the four 16-bit halfwords of register VB and writes the count (0-16) into the corresponding halfword of register VD. Does not affect CR or FPSCR.

Operation

for i in 0 to 3 do
  halfword ← VB[16*i : 16*i+15]
  VD[16*i : 16*i+15] ← ctz(halfword) // count leading zeros in 16-bit value

Programming Note

The vclzh instruction is useful for counting leading zeros in each halfword of a vector, which can be helpful in various bit manipulation tasks. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 8 halfwords per vector register, and results are stored directly in the destination vector register.