xscvudqp

VSX Scalar Convert Unsigned Doubleword to Quad-Precision

xscvudqp vD, vB

Converts 64-bit Unsigned Integer to 128-bit Float.

Encoding

Binary Layout

63

0:5

vD

6:10

/

11:15

vB

16:20

724

21:30

/

31

 

Format X-form

Opcode 0xFC020688

Extension VSX

Operands

• vD
  Target
• vB
  Source

Example

xscvudqp vd, vb

Registers Altered

FPSCR, MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts an unsigned 64-bit doubleword value from the source VSR into a 128-bit IEEE 754 quadruple-precision (quad) floating-point value and stores the result in the target VSR. This VSX scalar operation uses the default rounding mode from FPSCR and updates the floating-point status and control register (FPSCR) with exception flags if applicable. The instruction requires VSX facility enablement.

Operation

FRT ← ConvertUnsignedIntegerToQuadPrecision(FRB[0:63], FPSCR[RN])
FPSCR ← UpdateFlags(FPSCR)

Programming Note

This instruction is used to convert an unsigned doubleword integer into a quad-precision floating-point format. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. The conversion may alter the FPSCR register fields, so be aware of potential precision flags. This operation does not raise exceptions for normal input ranges.