xscmpodp

VSX Scalar Compare Ordered Double-Precision

xscmpodp BF, XA, XB

Compares two double-precision floating-point values and sets the condition register based on the comparison.

Encoding

Binary Layout

0:5

6:8

9:10

11:15

16:20

21:31

Format XX3-form

Opcode 0xF0000158

Extension VSX

Operands

BF
CR Field
XA
Src A
XB
Src B

Example

xscmpodp cr0, vs2, vs3

Registers Altered

CR, FPSCR, VXSNAN, VXVC

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs an ordered comparison of the double-precision floating-point values in XA and XB, setting the specified CR field (BF) with the comparison result: less-than, greater-than, equal, or unordered. If either operand is a signaling NaN, an invalid operation exception is raised in FPSCR. Quiet NaNs result in an unordered condition.

Operation

if isnan(XA[0:63]) | isnan(XB[0:63]) then
  FPSCR[VXVC] ← 1
  CR[BF*4:BF*4+3] ← 0001
elsif XA[0:63] < XB[0:63] then
  CR[BF*4:BF*4+3] ← 1000
elsif XA[0:63] > XB[0:63] then
  CR[BF*4:BF*4+3] ← 0100
else
  CR[BF*4:BF*4+3] ← 0010

Programming Note

This instruction can be used to operate on single-precision source operands.