xscmpodp

VSX Scalar Compare Ordered Double-Precision

xscmpodp BF, XA, XB

Compares two double-precision floating-point values and sets the condition register based on the comparison.

Details

The xscmpodp instruction compares the double-precision floating-point value in doubleword element 0 of VSR[XA] with the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is stored in the FPCC field of the FPSCR register and also reflected in CR[BF].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
if src1.class.SNaN=1 | src2.class.SNaN=1 then do
   vxsnan_flag ←0b1
   if FPSCR.VE=0 then vxvc_flag ←0b1
end
else
   vxvc_flag ←src1.class.QNaN | src2.class.QNaN
if vxvc_flag=1 then SetFX(FPSCR.VXVC)
CR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2
CR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2
CR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2
CR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN

Programming Note

This instruction can be used to operate on single-precision source operands.

Example

xscmpodp cr0, vs2, vs3

Encoding

Binary Layout
60
0
BF
6
/
9
XA
11
XB
16
43
21
 
Format XX3-form
Opcode 0xF000002B
Extension VSX
Registers Altered CR, FPSCR, VXSNAN, VXVC

Operands

  • BF
    CR Field
  • XA
    Src A
  • XB
    Src B