vextuhlx

Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index

vextuhlx RT,RA,VRB

Extracts an unsigned halfword from a vector register and places it into a general-purpose register using the left index specified in another general-purpose register.

Encoding

Binary Layout

0:5

6:10

11:15

VRB

16:31

Format VX-form

Opcode 0x1000064D

Extension VMX (AltiVec)

Operands

RT
Target General Purpose Register
RA
Source General Purpose Register
VRB
Vector Register

Example

vextuhlx r3, r4, v3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction extracts an unsigned halfword from VSR[VRB+32] based on the left index specified in bits 60:63 of GPR[RA]. The extracted halfword is placed into bits 48:63 of GPR[RT], and bits 0:47 of GPR[RT] are set to zero. If the index is greater than 14, the results are undefined.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RA].bit[60:63]
GPR[RT] ← EXTZ64(VSR[VRB+32].byte[index:index+1])
if index > 14 then
    undefined

Programming Note

This instruction is used to extract an unsigned halfword from a vector register into a general-purpose register. Ensure the left index specified in bits 60:63 of GPR[RA] does not exceed 14 to avoid undefined behavior. The result is zero-extended to 64 bits, so only the upper 16 bits of GPR[RT] will contain valid data.