vextduhvlx

Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form

vextduhvlx VRT,VRA,VRB,RC

Extracts a double unsigned halfword from two vector registers and places it into another vector register based on the index specified in a general-purpose register.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRA

11:15

VRB

16:20

RC

21:25

26

26:31

 

Format VA-form

Opcode 0x1000001A

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register
• RC
  General Purpose Register specifying the index

Example

vextduhvlx v1, v2, v3, r6

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction extracts a double unsigned halfword from the concatenation of VSR[VRA+32] and VSR[VRB+32] using the index specified in bits 59:63 of GPR[RC]. The extracted byte elements are zero-extended and placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index:index+1])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

Programming Note

This instruction is used to extract a double unsigned halfword from two vector registers and place it into another vector register. Ensure that the index specified in GPR[RC] is within bounds to avoid undefined behavior. The operation requires the VEC bit in the MSR to be set; otherwise, a Vector Unavailable exception will occur.