vmulosw

Vector Multiply Odd Signed Word

vmulosw vD, vA, vB

Multiplies odd words (1,3) to 64-bit signed result.

Details

The vmulosw instruction multiplies the signed integers in odd word elements of two vector registers and stores the 64-bit products in doubleword elements of a result vector register.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 1
   src1 ←EXTS(VSR[VRA+32].word[2×i+1])
   src2 ←EXTS(VSR[VRB+32].word[2×i+1])
   VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

Programming Note

The vmulosw instruction is used for multiplying signed integers located in the odd word elements of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in doubleword elements of the destination register, and developers should handle potential overflow by checking the sign extension of the products.

Example

vmulosw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
392
21
 
Format VX-form
Opcode 0x10000188
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B