vmulosw

Vector Multiply Odd Signed Word

vmulosw vD, vA, vB

Multiplies odd words (1,3) to 64-bit signed result.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

392

21:31

 

Format VX-form

Opcode 0x10000188

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vmulosw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the signed 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two signed 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

Operation

vD[0:63] ← (vA[32:63] signed) × (vB[32:63] signed)
vD[64:127] ← (vA[96:127] signed) × (vB[96:127] signed)

Programming Note

The vmulosw instruction is used for multiplying signed integers located in the odd word elements of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result is stored in doubleword elements of the destination register, and developers should handle potential overflow by checking the sign extension of the products.