vmulld

Vector Multiply Low Doubleword

vmulld VRT,VRA,VRB

Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.

Details

For vmulld, the integer values in doubleword elements of VSR[VRA+32] are multiplied by the corresponding integer values in doubleword elements of VSR[VRB+32]. The low-order 64 bits of each product are placed into doubleword elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

Programming Note

This instruction multiplies the integer values in doubleword elements of two vector registers and stores the low-order 64 bits of each product into another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes two doublewords per iteration, so be cautious with loop bounds if using this in a larger computation.

Example

vmulld v1, v2, v3

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x100001C9
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register