vmulld

Vector Multiply Low Doubleword

vmulld VRT,VRA,VRB

Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:31

Format VX-form

Opcode 0x100001C9

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmulld v1, v2, v3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmulld, the integer values in doubleword elements of VSR[VRA+32] are multiplied by the corresponding integer values in doubleword elements of VSR[VRB+32]. The low-order 64 bits of each product are placed into doubleword elements of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

Programming Note

This instruction multiplies the integer values in doubleword elements of two vector registers and stores the low-order 64 bits of each product into another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation processes two doublewords per iteration, so be cautious with loop bounds if using this in a larger computation.