stvx

Store Vector Indexed

stvx vS, RA, RB

Stores a quadword from a vector register to memory at an address formed by adding two general-purpose registers.

Encoding

Binary Layout

31

0:5

vS

6:10

RA

11:15

RB

16:20

231

21:30

/

31

 

Format X-form

Opcode 0x7C0001CE

Extension VMX (AltiVec)

Operands

• vS
  Source Vector Register
• RA
  Base Register
• RB
  Index Register
• VRS
  Vector Register

Example

stvx v1, r3, r4

// Store aligned vector.

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of VSR[VRS+32] are placed into the quad-word in storage at address EA, which is the result of ANDing 0xFFFF_FFFF_FFFF_FFF0 with the sum (RA|0) + (RB).

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
EA ←EA & 0xFFFF_FFFF_FFFF_FFF0
MEM(EA, 16) ←VSR[VRS+32]

Programming Note

The stvx instruction stores a vector register into memory. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register if necessary. The effective address (EA) must be aligned to a 16-byte boundary, as indicated by the AND operation with 0xFFFF_FFFF_FFFF_FFF0. This instruction operates at user privilege level but will raise an exception if the Vector Facility is not available.