vmuloub

Vector Multiply Odd Unsigned Byte

vmuloub vD, vA, vB

Multiplies odd unsigned bytes to halfwords.

Encoding

Binary Layout

00000

0:5

001000

6:15

VRT

16:20

VRA

21:25

VRB

26:31

Format VX-form

Opcode 0x10000008

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register A
VRB
Source Vector Register B

Example

vmuloub vd, va, vb

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the odd-indexed unsigned bytes from vA and vB, producing unsigned halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating eight halfword products without sign extension. No condition flags are affected.

Operation

vD[0:15] ← (vA[8:15] × vB[8:15]) as unsigned
vD[16:31] ← (vA[24:31] × vB[24:31]) as unsigned
vD[32:47] ← (vA[40:47] × vB[40:47]) as unsigned
vD[48:63] ← (vA[56:63] × vB[56:63]) as unsigned
vD[64:79] ← (vA[72:79] × vB[72:79]) as unsigned
vD[80:95] ← (vA[88:95] × vB[88:95]) as unsigned
vD[96:111] ← (vA[104:111] × vB[104:111]) as unsigned
vD[112:127] ← (vA[120:127] × vB[120:127]) as unsigned

Programming Note

This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors. Ensure that the input vectors are properly aligned to avoid unexpected results. The operation does not require any special privileges, but it's important to handle potential overflow by zero-extending the 8-bit result to 16 bits.