vpermr

Vector Permute Right

vpermr vD, vA, vB, vC

Bitwise byte shuffle similar to vperm but for little-endian access optimization.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:25

26:31

Format VA-form

Opcode 0x1000003B

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
vC
Permute
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vpermr vd, va, vb, vc

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a byte permutation by selecting bytes from the concatenation of vA and vB using indices from vC, optimized for little-endian access patterns. This VMX/AltiVec instruction rearranges 16 bytes across the three source registers and stores the result in vD, with no impact on condition registers.

Operation

src ← vA || vB
for i in 0 to 15:
  index ← vC[4*i:4*i+3]
  vD[8*i:8*i+7] ← src[8*index:8*index+7]

Programming Note

The vpermr instruction is used to perform a right permutation on the elements of a vector register. It is commonly used in scenarios where data needs to be shifted or rotated within a vector for operations like cryptography, signal processing, or custom algorithms. Ensure that the input vector is properly aligned and that the operation does not exceed the bounds of the vector register to avoid undefined behavior. This instruction operates at user privilege level and may raise exceptions if the alignment requirements are not met.