vcmpgtsd.

Vector Compare Greater Than Signed Doubleword (Record)

vcmpgtsd. VRT,VRA,VRB

Compares two doublewords of signed integers and sets the result vector based on the comparison.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x100003C7

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpgtsd v1, v2, v3

Registers Altered

CR6 (if Rc=1)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpgtsd, each doubleword in VSR[VRA+32] is compared to the corresponding doubleword in VSR[VRB+32]. If a doubleword in VSR[VRA+32] is greater than the corresponding doubleword in VSR[VRB+32], the corresponding doubleword in VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

Operation

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    if src1 > src2 then do
        VSR[VRT+32].dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].dword[i] ←0x0000_0000_0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.