vcmpgtsh.

Vector Compare Greater Than Signed Halfword (Record)

vcmpgtsh. VRT,VRA,VRB

Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.

Encoding

Binary Layout

VRT

VRA

VRB

Format VC-form

Opcode 0x10000346

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpgtsh v1, v2, v3

Registers Altered

CR6 (if Rc=1)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpgtsh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If the signed value in VSR[VRA+32].hword[i] is greater than that in VSR[VRB+32].hword[i], then VSR[VRT+32].hword[i] is set to 0xFFFF; otherwise, it is set to 0x0000.

Operation

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    if src1 > src2 then do
        VSR[VRT+32].hword[i] ←0xFFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].hword[i] ←0x0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.