vcmpgtuw

Vector Compare Greater Than Unsigned Word

vcmpgtuw vD, vA, vB

Unsigned > comparison for 4 words.

Details

The Vector Compare Greater Than Unsigned Word instruction compares each unsigned word element of two vector registers and sets the corresponding result elements to all 1s if the first operand is greater than the second, otherwise to all 0s. If Rc=1, it also updates CR field 6 to indicate whether all elements compared true or false.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].word[i])
   src2 ←EXTZ(VSR[VRB+32].word[i])
   if src1 > src2 then do
      VSR[VRT+32].word[i] ←0xFFFFFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x00000000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

This instruction is commonly used for element-wise comparison of unsigned integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result register must be aligned to 128 bits, and both source registers should contain valid data. If Rc=1, CR field 6 will reflect whether all comparisons were true or false, which can be useful for conditional branching based on vector comparison results.

Example

vcmpgtuw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
646
21
 
Format VC-form
Opcode 0x10000286
Extension VMX (AltiVec)
Registers Altered MSR, CR6

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B