vcmpgtuw

Vector Compare Greater Than Unsigned Word

vcmpgtuw vD, vA, vB

Unsigned > comparison for 4 words.

Details

Performs an unsigned greater-than comparison of two vector registers on a word-by-word basis (4 words) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

Pseudocode Operation

for i in 0 to 3 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF_FFFF
  else
    vD[i] ← 0x0000_0000

Programming Note

This instruction is commonly used for element-wise comparison of unsigned integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The result register must be aligned to 128 bits, and both source registers should contain valid data. If Rc=1, CR field 6 will reflect whether all comparisons were true or false, which can be useful for conditional branching based on vector comparison results.

Example

vcmpgtuw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
646
21
 
Format VC-form
Opcode 0x10000286
Extension VMX (AltiVec)
Registers Altered MSR, CR6

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B