slw.

Shift Left Word Immediate

slw. RT,RA,RB

Shifts the contents of a register left by a specified number of bits and updates the condition register.

Encoding

Binary Layout

18

0:5

LI

6:29

AA

30

LK

31

 

Format XO-form

Opcode 0x7C000030

Extension Base

Operands

• RT
  Target General Purpose Register
• RA
  Source General Purpose Register
• RB
  Shift Count (0-31)

Example

slw. r3, r4, r5

Registers Altered

CR0, XER

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For slw., the contents of register RA are shifted left by the amount specified in RB, and the result is placed into register RT. The shift count is masked to 5 bits.

Operation

if 'slw.' then
    RT <- (RA) << ((RB) & 31)

Programming Note

The slw instruction shifts the contents of RA left by a number of bits specified in RB, with the shift count masked to 5 bits. This operation is useful for bit manipulation tasks but be cautious as shifting large values can lead to overflow. The result is stored in RT, and this instruction operates at user privilege level.