scv

System Call Vectored

scv LEV

Performs a system call to a fixed vector address (Faster than 'sc').

Details

The scv instruction generates a System Call Vectored interrupt. The effective address of the instruction following the scv instruction is placed into the Link Register. Bits 0:32, 37:41, and 48:63 of the MSR are placed into the corresponding bits of Count Register, and bits 33:36 and 42:47 of Count Register are set to undefined values.

Pseudocode Operation

NIA ← (see below)
if the new MSR value does not enable any pending exceptions, then
    fetch next instruction from LR0:61 || 0b00 (when SF=1) or 320 || LR32:61 || 0b00 (when SF=0)
else
generate interrupt associated with the highest priority pending exception

Programming Note

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0. This instruction does not alter MSRHV, MSRS, or MSRME.

Example

scv 0

Encoding

Binary Layout
0
0
6
6
11
11
16
16
20
20
27
27
30
30
31
31
 
Format SC-form
Opcode 0x44000002
Extension Base
Registers Altered LR, CTR, MSR

Operands

  • LEV
    Level