scv

System Call Vectored

scv LEV

Performs a system call to a fixed vector address (Faster than 'sc').

Encoding

Binary Layout

Format SC-form

Opcode 0x44000001

Extension Base

Operands

LEV
Level

Example

scv 0

Registers Altered

LR, CTR, MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Perform a system call with a vectored trap to a fixed address determined by the LEV (level) field, providing faster dispatch than the traditional sc instruction. The instruction saves SRR0 and SRR1, sets MSR[PR]=0 to enter privileged mode, and jumps to the system call vector. LEV is a 7-bit field (bits 20-26) that selects among up to 128 vector addresses.

Operation

SRR0 ← CIA + 4
SRR1 ← MSR
MSR[PR] ← 0
MSR[EE] ← 0
MSR[IR] ← 0
MSR[DR] ← 0
PC ← Interrupt Vector Base + (LEV << 7) + System Call Vectored Offset

Programming Note

If this instruction sets MSRPR to 1, it also sets MSREE, MSRIR, and MSRDR to 1. If this instruction results in MSRS HV PR being equal to 0b110, it also sets MSRIR and MSRDR to 0. This instruction does not alter MSRHV, MSRS, or MSRME.

scv