plha

Prefixed Load Halfword Algebraic

plha RT, D(RA), R

Loads 16-bit halfword (Sign Extended) using 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

42

32:37

RT

38:42

RA

43:47

D1

48:63

 

Format MLS:D-form

Opcode 0x06000000A8000000

Extension Prefixed

Operands

• RT
  Target
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

plha r3, 0(r4), 0

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 16-bit halfword from memory using a 34-bit signed offset (split between prefix and suffix), sign-extends the loaded value to 64 bits, and stores the result in the target register. The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed load with no condition register or status flag effects.

Operation

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
RT ← EXTS(MEM(EA, 2))

Programming Note

The plha instruction is commonly used for loading a halfword from memory into the upper half of a register while zeroing out the lower half. Ensure that the base and index registers are correctly set to avoid incorrect memory access. This instruction operates at user privilege level and may raise an exception if the effective address is invalid or if there's a protection fault.