xsdivsp

VSX Scalar Divide Single-Precision

xsdivsp XT, XA, XB

Divides the contents of two doubleword elements in VSX registers and places the result in a single-precision format.

Details

The instruction divides the double-precision floating-point value in doubleword element 0 of VSR[XB] by the double-precision floating-point value in doubleword element 0 of VSR[XA]. The quotient is normalized, rounded to single-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v    ←bfp_DIVIDE(src1,src2)
rnd      ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxidi_flag=1 then SetFX(FPSCR.VXIDI)
if vxzdz_flag=1 then SetFX(FPSCR.VXZDZ)
vx_flag  ←vxsnan_flag | vxidi_flag | vxzdz_flag
vex_flag ←FPSCR.VE & vx_flag
zex_flag ←FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
   VSR[32×TX+T].dword[0] ←result64
   VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
   FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
   FPSCR.FR  ←inc_flag
   FPSCR.FI  ←xx_flag
else do
   FPSCR.FR  ←0b0
   FPSCR.FI  ←0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsdivsp vs1, vs2, vs3

Encoding

Binary Layout

111100

000000

Format XX3-form

Opcode 0xF0000018

Extension VSX

Registers Altered FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

Operands

XT
Target
XA
Src A
XB
Src B