lxvw4x

Load VSX Vector Word*4 Indexed

lxvw4x XT, RA, RB

Loads four words into a vector (unaligned).

Details

The contents of the byte in storage at address EA+4×i+3 are placed into byte element 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA+4×i are placed into word element i of VSR[XT] in such an order that; if MSR.VSX=0 then VSX_Unavailable(). EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]. Let XT be the value 32×TX + T. Let EA be the sum of the contents of GPR[RA], or 0 if RA is equal to 0, and the contents of GPR[RB]. For each integer value i from 0 to 3, do the following.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
for i from 0 to 3 do
    VSR[32×TX+T].word[i] ←MEM(EA+4×i, 4)

Programming Note

lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.

Example

lxvw4x vs1, r4, r5

Encoding

Binary Layout

780

Format XX1-form

Opcode 0x7C00030C

Extension VSX

Registers Altered MSR

Operands

XT
Target
RA
Base
RB
Index