vmladduhm

Vector Multiply-Low-Add Unsigned Halfword Modulo

vmladduhm VRT,VRA,VRB,VRC

Performs a vector multiply-low-add unsigned halfword modulo operation.

Encoding

Binary Layout
1
VRT
VRA
VRB
VRC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
 
Format VA-form
Opcode 0x10000022
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VRC
    Source Vector Register

Example

vmladduhm v1, v2, v3, v4

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For each integer value i from 0 to 7, the unsigned integer value in halfword element i of VSR[VRA+32] is multiplied by the unsigned integer value in halfword element i in VSR[VRB+32]. The product is added to the unsigned integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the sum are placed into halfword element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTZ(VSR[VRA+32].hword[i])
    src2 ←EXTZ(VSR[VRB+32].hword[i])
    src3 ←EXTZ(VSR[VRC+32].hword[i])
    VSR[VRT+32].hword[i] ← CHOP16((src1 × src2) + src3)
end

Programming Note

vmladduhm can be used for unsigned or signed integers.