xscmpexpdp

VSX Scalar Compare Exponents Double-Precision

xscmpexpdp BF, XA, XB

Compares the exponents of two double-precision floating-point values in VSX registers and updates the condition register.

Encoding

Binary Layout

60

0:5

BF

6:10

/

11:15

XA

16:20

XB

21:30

59

31

 

Format XX3-form

Opcode 0xF00001D8

Extension VSX

Operands

• BF
  CR Field
• XA
  Src A
• XB
  Src B

Example

xscmpexpdp cr0, vs2, vs3

Registers Altered

CR, FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The exponent of src1 is compared with the exponent of src2. The result of the compare is placed into FPCC and CR field BF.

Operation

if MSR.VSX=0 then VSX_Unavailable()
src1 ←VSR[32×AX+A].dword[0]
src2 ←VSR[32×BX+B].dword[0]
src1.exponent ←EXTZ(src1.bit[1:11])
src1.fraction ←EXTZ(src1.bit[12:63])
src2.exponent ←EXTZ(src2.bit[1:11])
src2.fraction ←EXTZ(src2.bit[12:63])
src1.class.NaN ←(src1.exponent = 2047) & (src1.fraction != 0)
src2.class.NaN ←(src2.exponent = 2047) & (src2.fraction != 0)
lt_flag ←(src1.exponent < src2.exponent)
gt_flag ←(src1.exponent > src2.exponent)
eq_flag ←(src1.exponent = src2.exponent)
uo_flag ←src1.class.NaN | src2.class.NaN
CR.bit[4×BF+32] ←FPSCR.FL ←!uo_flag & lt_flag
CR.bit[4×BF+33] ←FPSCR.FG ←!uo_flag & gt_flag
CR.bit[4×BF+34] ←FPSCR.FE ←!uo_flag & eq_flag
CR.bit[4×BF+35] ←FPSCR.FU ←uo_flag

Programming Note

This instruction can be used to operate on single-precision source operands.