stfdux

Store Floating-Point Double with Update Indexed

stfdux FRS,RA,RB

Stores the contents of a floating-point register into memory and updates the base address register.

Encoding

Binary Layout

0

0:5

FRS

6:10

RA

11:15

RB

16:31

 

Format X-form

Opcode 0x7C0005EE

Extension Floating-Point

Operands

• FRS
  Floating-Point Register Source
• RA
  General Purpose Register Address
• RB
  General Purpose Register Index

Example

stfdux f1, r4, r5

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of register FRS are stored into the double-word in storage addressed by EA. The effective address (EA) is the sum of the contents of registers RA and RB. If RA=0, the instruction form is invalid. EA is placed back into register RA.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
MEM(EA, 8) ← (FRS)
RA ← EA

Programming Note

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.