frip.

Floating Round to Integer Plus (Record)

frip. FRT,FRB

Rounds a floating-point operand towards +infinity and places the result into a register.

Encoding

Binary Layout

0

0:5

FRT

6:10

FRB

11:30

Rc

31

 

Format X-form

Opcode 0xFC000390

Extension Floating-Point

Operands

• FRT
  Target Floating-Point Register
• FRB
  Source Floating-Point Register

Example

frip f1, f3

Registers Altered

FPSCR, CR, CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The floating-point operand in register FRB is rounded to an integral value using the rounding mode round toward +infinity, and the result is placed into register FRT. FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.

Operation

if 'frip' then
    FRT <- round_towards_plus_infinity(FRB)
else if 'frip.' then
    FRT <- round_towards_plus_infinity(FRB)
    update_CR1_based_on_result(FRT)

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.