lfdu

Load Floating-Point Double with Update

lfdu FRT,D(RA)

Loads a doubleword from memory into a floating-point register and updates the base address register.

Encoding

Binary Layout

0

0:5

FRT

6:10

RA

11:15

D

16:31

 

Format D-form

Opcode 0xCC000000

Extension Floating-Point

Operands

• FRT
  Target Floating Point Register
• RA
  Base General Purpose Register
• D
  Displacement

Example

lfdu f1, 0(r4)

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The doubleword in storage addressed by EA is loaded into register FRT. The effective address (EA) is the sum of the contents of register RA, or the value 0 if RA=0, and the value D, sign-extended to 64 bits. If RA=0, the instruction form is invalid.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + EXTS(D)
FRT ← MEM(EA, 8)
RA ← EA

Programming Note

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.