PowerISA Instructions

1135 instructions — click any row to view encoding, pseudocode, and full documentation.

Mnemonic ⇅	Syntax	Format ⇅	Extension ⇅	Summary
add	add RT, RA, RB	XO-form	Base	Adds the contents of two registers and places the result in a third register.
add.	add. RT,RA,RB	XO-form	Base	Adds the contents of two registers and updates the condition register.
addc	addc RT,RA,RB addc. RT,RA,RB addco RT,RA,RB addco. RT,RA,RB	XO-form	Base	Adds the contents of two registers and a carry bit, placing the result in a target register.
adde	adde RT, RA, RB	XO-form	Base	Adds two registers plus the current Carry bit.
addex	addex RT,RA,RB,CY	XO-form	Base	Adds the contents of two registers and an alternate carry bit, updating the condition register.
addg6s	addg6s RT,RA,RB	XO-form	Base	Adds the contents of two registers and generates sixes based on carry bits.
addi	addi RT, RA, SI	D-form	Base	Adds a signed immediate value to the contents of a register and places the result in another register.
addic	addic RT,RA,SI subf RT,RA,RB subf. RT,RA,RB subfo RT,RA,RB subfo. RT,RA,RB	D-form	Base	Adds an immediate to a register and updates the Carry bit.
addic.	addic. RT, RA, SI	D-form	Base	Adds an immediate, updates Carry, and updates Condition Register Field 0 (CR0).
addis	addis RT, RA, SI	D-form	Base	Adds an immediate value shifted left by 16 bits to the contents of a register and places the result in another register.
addme	addme RT,RA addme. RT,RA addmeo RT,RA addmeo. RT,RA	XO-form	Base	Adds the contents of a register and a constant minus one, with optional overflow exception.
addme.	addme. RT,RA,RB	XO-form	Base	Adds the contents of two registers and subtracts one, then updates the condition register.
addze	addze RT, RA	XO-form	Base	Adds a register, 0, and the Carry bit.
and	and RT,RS,RB and. RT,RS,RB	X-form	Base	Performs a bitwise AND operation on the contents of two registers and places the result into another register.
andc	andc RA, RS, RB	X-form	Base	Performs a bitwise AND between RS and the one's complement of RB.
andi.	andi. RA, RS, UI	D-form	Base	Performs a bitwise AND operation between the contents of a register and an immediate value, and updates the condition register.
andis.	andis. RA, RS, UI	D-form	Base	Performs a bitwise AND between a register and a 16-bit immediate shifted left by 16 bits. Always updates CR0.
attn	attn	X-form	Privileged	Stops execution and alerts the hardware debugger.
b	b target_addr (AA=0 LK=0) b+ target_addr (AA=1 LK=0) ba target_addr (AA=0 LK=1) ba+ target_addr (AA=1 LK=1)	I-form	Base	Unconditionally branches to a target address relative to the current instruction pointer.
ba	ba target_addr	I-form	Base	Unconditionally branches to an absolute address.
bc	bc BO,BI,target_addr (AA=0 LK=0) bc BO,BI,target_addr (AA=1 LK=0) bc BO,BI,target_addr (AA=0 LK=1) bc BO,BI,target_addr (AA=1 LK=1)	B-form	Base	Branches conditionally based on the Count Register (CTR) and/or a bit in the Condition Register (CR).
bcctr	bcctr BO, BI	XL-form	Base	Branches to the address in the Count Register (CTR) if the condition is met. Used for computed jumps and switch statements.
bcdadd.	bcdadd. VRT,RA,RB	XO-form	Decimal Floating-Point	Adds two packed decimal integers and updates the condition register.
bcdcfn.	bcdcfn. vD, vB, PS	VX-form	Vector BCD	Converts a national decimal value to packed decimal format and stores it in the target vector register.
bcdcfsq.	bcdcfsq. vD, vB, PS	VX-form	Vector BCD	Converts a signed quadword integer to packed decimal format and updates the condition register.
bcdcfz.	bcdcfz. vD, vB, PS	VX-form	Vector BCD	Converts BCD Zoned format to Signed Packed BCD.
bcdcpsgn.	bcdcpsgn. VRT,VRA,VRB	VX-form	Decimal Floating-Point	Copies the sign of a decimal value from one register to another while preserving the magnitude.
bcdctn.	bcdctn. vD, vB	VX-form	Vector BCD	Converts a packed decimal value to national decimal format and stores it in a vector register.
bcdctsq.	bcdctsq. vD, vB	VX-form	Vector BCD	Compares two binary coded decimal (BCD) numbers in a quadword format and tests the sign.
bcdctz.	bcdctz. vD, vB, PS	VX-form	Vector BCD	Converts Signed Packed BCD to Zoned format.
bcds.	bcds. VRT,VRA,VRB,PS	VX-form	Decimal Floating-Point	Shifts a signed packed decimal value by a specified number of digits and rounds the result.
bcdsetsgn.	bcdsetsgn. VRT,VRB,PS	VX-form	Decimal Floating-Point	Sets the sign of a packed decimal value in a vector register based on the specified conditions.
bcdsr.	bcdsr. VRT,VRA,VRB,PS	VX-form	VMX (AltiVec)	Shifts a binary coded decimal value by a specified number of digits and rounds the result.
bcdtrunc.	bcdtrunc. VRT,VRA,VRB,PS	VX-form	Decimal Floating-Point	Truncates a decimal value to a specified length and updates the condition register.
bcdus.	bcdus. VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs an unsigned shift on packed decimal values in vector registers.
bcdutrunc.	bcdutrunc. VRT,VRA,VRB	VX-form	VMX (AltiVec)	Truncates the unsigned decimal value in VRB to a specified length and places it into VRT.
bclr	bclr BO,BI,BH bclrl BO,BI,BH	XL-form	Base	Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.
bctar	bctar BO,BI,BH (LK=0)	XL-form	Base	Conditional branch based on the contents of the Condition Register and the Count Register.
bl	bl target_addr	I-form	Base	Branches to a target address and saves the return address (CIA + 4) in the Link Register (LR). Used for function calls.
blt	blt target blta target bltlr clears LR bltctr clears CTR	B-form	Base	Branches to a target address if the condition 'less than' is true.
blt+	blt+ target	B-form	Base	Branches to the target address if CR0 reflects condition 'less than', predicting the branch will be taken.
bpermd	bpermd RA, RS, RB	X-form	Base	Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.
brd	brd RT,RA	XO-form	Base	Reverses the bytes in a doubleword.
brh	brh RA,RS	X-form	Base	Reverses the byte order of a halfword in a register.
cfuged	cfuged RA, RS, RB	X-form	Base	Separates bits of the source register into two groups based on a mask (Power10 Scalar).
clrbhrb	clrbhrb	X-form	Base	Clear Branch History Rolling Buffer. Clears all entries in the Branch History Rolling Buffer (BHRB) to zero. Used to flush branch prediction history, for example when switching execution contexts to prevent information leakage between security domains.
cmp	cmp BF, L, RA, RB	X-form	Base	Compares two registers as signed integers and records the result in the specified Condition Register Field.
cmpb	cmpb RA, RS, RB	X-form	Base	Compares bytes in two GPRs, result is byte mask.
cmpdi	cmpdi bf,ra,si	XO-form	Base	Compares a doubleword immediate value with the contents of a register and updates the condition register.
cmpeqb	cmpeqb RA, RS, RB	X-form	Base	Compares the contents of bits 56:63 of register RA with each byte in register RB and sets the condition register field BF.
cmpi	cmpi BF, L, RA, SI	D-form	Base	Compares the contents of register RA with a sign-extended immediate value.
cmpl	cmpl BF, L, RA, RB	X-form	Base	Compares two registers as unsigned integers.
cmpli	cmpli BF, L, RA, UI	D-form	Base	Compares the contents of a register with an immediate value and updates the condition register.
cmprb	cmprb BF, L, RA, RB	X-form	Base	Compares a byte value in one register to see if it falls within a range defined by another register.
cntlzd	cntlzd RT,RA cntlzd. RT,RA	X-form	Base	Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).
cntlzdm	cntlzdm RA, RS, RB	X-form	Base	Counts leading zeros in RS, but only considering bits set in mask RB.
cntlzw	cntlzw RA, RS	X-form	Base	Counts the number of consecutive 0 bits starting from bit 32 (MSB of the low word).
cnttzd	cnttzd RA, RS	X-form	Base	Counts the number of trailing zeros in 64-bits.
cnttzdm	cnttzdm RA, RS, RB	X-form	Base	Counts trailing zeros in RS, but only considering bits set in mask RB.
cnttzw	cnttzw RA, RS	X-form	Base	Counts the number of trailing zeros in the low 32-bits.
copy	copy RA, RB	X-form	Privileged	Initiates a hardware copy (accelerator) operation.
cp_abort	cp_abort	X-form	Privileged	Aborts a hardware accelerator copy-paste sequence.
cpabort	cpabort	X-form	Base	Aborts any in-progress copy-paste operation, discarding any pending copy target set by a previous Copy instruction.
crand	crand BT, BA, BB	XL-form	Base	Performs a bitwise AND between two bits in the Condition Register.
crc32b	crc32b RA, RS	X-form	Base	Accumulates a CRC32 checksum using the low byte of RS.
crc32d	crc32d RA, RS	X-form	Base	Accumulates a CRC32 checksum using the doubleword in RS.
crc32h	crc32h RA, RS	X-form	Base	Accumulates a CRC32 checksum using the low halfword of RS.
crc32w	crc32w RA, RS	X-form	Base	Accumulates a CRC32 checksum using the word in RS.
creqv	creqv CRb,CRA,CRB	XL-form	Base	Sets the condition register field to 1 if the corresponding fields of two source registers are equal, otherwise sets it to 0.
crnor	crnor BT,BA,BB	XL-form	Base	Performs a bitwise NOR operation on the specified bits of the Condition Registers and stores the result in another bit of the Condition Register.
cror	cror BT, BA, BB	XL-form	Base	Performs a bitwise OR between two bits in the Condition Register.
crxor	crxor BT, BA, BB	XL-form	Base	Performs a bitwise XOR between two bits in the Condition Register. Used to clear CR bits (crxor x,x,x).
ctfix	ctfix FRT,FRA	X-form	Decimal Floating-Point	Converts a decimal floating-point value to a fixed-point integer.
dadd	dadd FRT,FRA,FRB Rc=0	X-form	Decimal Floating-Point	Adds two 64-bit Decimal Floating Point (DFP) numbers. Used in financial calculations to avoid rounding errors.
dadd.	dadd. FRD,FRB,FRC	XO-form	Base	Adds the contents of two double precision floating-point registers and updates the condition register.
daddq	daddq vD, vA, vB	X-form	Decimal Floating-Point	Adds two 128-bit DFP numbers.
darn	darn RT, L	X-form	Base	Returns a random number from the hardware RNG. (L=3: Raw, L=1: Conditioned, L=0: 32-bit).
dcba	dcba RA, RB	X-form	Base	Allocates a cache block without loading from memory (optimization for overwrite).
dcbf	dcbf RA,RB,L dcbfl RA,RB dcbflp RA,RB dcbfps RA,RB dcbstps RA,RB	X-form	Base	Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.
dcbi	dcbi RA, RB	X-form	Privileged	Invalidates a cache block (Privileged).
dcblc	dcblc CT, RA, RB	X-form	Embedded	Clears a cache line lock.
dcbst	dcbst RA, RB	X-form	Base	Writes the cache block to main memory if it is modified (Clean), but keeps it in the cache.
dcbt	dcbt RA,RB,TH dcbtt RA,RB dcbna RA,RB dcbtds RA,RB,TH	X-form	Base	Hints to the hardware to prefetch the cache block at the specified address into the cache.
dcbtls	dcbtls CT, RA, RB	X-form	Privileged	Locks a cache line in the L1 cache.
dcbtst	dcbtst TH, RA, RB	X-form	Base	Provides a hint that describes a block or data stream to which the program may perform a store access.
dcbz	dcbz RA, RB	X-form	Base	Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).
dcbzl	dcbzl RA, RB	X-form	Base	Zeros a cache block (implementation defined size).
dccci	dccci RA, RB	X-form	Embedded	Invalidates a congruence class in the data cache (Embedded).
dcffi	dcffi FRT,FRB Rc=0	X-form	Decimal Floating-Point	Converts a 64-bit signed binary integer to a DFP Long value.
dcffix	dcffix FRT, FRB	X-form	Decimal Floating-Point	Converts a 64-bit integer to DFP.
dcffixq	dcffixq vD, vB	X-form	Decimal Floating-Point	Converts 64-bit integer to 128-bit DFP.
dcffixqq	dcffixqq RT,RA	X-form	Floating-Point	Converts a double-precision floating-point value to a quadword integer.
dcmpo	dcmpo BF, FRA, FRB	X-form	Decimal Floating-Point	Compares two decimal floating-point operands and updates the condition register.
dcmpoq	dcmpoq BF, vA, vB	X-form	Decimal Floating-Point	Compares two DFP values and sets the condition register based on their order.
dcmpu	dcmpu BF, FRA, FRB	X-form	Decimal Floating-Point	Compares two DFP operands and sets the CR field to indicate the result.
dcmpuq	dcmpuq BF, vA, vB	X-form	Decimal Floating-Point	Compares two 128-bit DFP numbers (Non-signaling).
dcread	dcread RT, RA, RB	X-form	Embedded	Reads a data cache tag or data (Debug).
dctdp	dctdp FRT, FRB	X-form	Decimal Floating-Point	Converts DFP Short (32-bit compressed) to DFP Long (64-bit).
dctfix	dctfix FRT,FRB dctfix. FRT,FRB	X-form	Decimal Floating-Point	Converts a decimal floating-point number to a fixed-point integer.
dctfixq	dctfixq vD, vB	X-form	Decimal Floating-Point	Converts 128-bit DFP to 64-bit integer.
dctqpq	dctqpq vD, FRB	X-form	Decimal Floating-Point	Converts DFP Long (64-bit) to DFP Quad (128-bit).
ddedpd	ddedpd SP,FRT,FRB ddedpd. SP,FRT,FRB	X-form	Decimal Floating-Point	Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.
ddedpdq	ddedpdq vD, vB, SP	X-form	Decimal Floating-Point	Decodes BCD to 128-bit DFP.
ddiv	ddiv FRT,FRA,FRB ddiv. FRT,FRA,FRB	X-form	Decimal Floating-Point	Divides the contents of two decimal floating-point registers and places the result in a target register.
ddivq	ddivq vD, vA, vB	X-form	Decimal Floating-Point	Divides two 128-bit DFP numbers.
denbcd	denbcd FRT, FRB, S	X-form	Decimal Floating-Point	Encodes a DFP number into BCD format.
denbcdq	denbcdq vD, vB, S	X-form	Decimal Floating-Point	Encodes 128-bit DFP to BCD.
dfadd	dfadd DRT,DSRC1,DSRC2	X-form	Decimal Floating-Point	Adds two decimal floating-point numbers.
diex	diex FRT, FRA, FRB	X-form	Decimal Floating-Point	Combines a sign/coefficient from FRA and exponent from FRB.
diexq	diexq vD, vA, vB	X-form	Decimal Floating-Point	Inserts exponent into 128-bit DFP.
diexq.	diexq. RT,RA,RB	X-form	Decimal Floating-Point	Inserts the biased exponent from a source register into a destination register in quad format.
divd	divd RT,RA,RB OE=0 Rc=0	XO-form	Base	Divides the contents of two registers and places the quotient into a target register.
divde	divde RT, RA, RB	XO-form	Base	Divides the contents of two registers and updates the condition register.
divdeu	divdeu RT, RA, RB	XO-form	Base	64-bit extended unsigned division.
divdu	divdu RT, RA, RB	XO-form	Base	Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).
divsq	divsq vD, vA, vB	VX-form	Base	Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).
divuq	divuq vD, vA, vB	VX-form	Base	Divides a 128-bit unsigned integer by a 128-bit unsigned integer.
divw	divw RT, RA, RB	XO-form	Base	Divides the contents of two registers and places the quotient into a target register.
divwe	divwe RT, RA, RB	XO-form	Base	Performs a signed division of a 64-bit dividend by a 32-bit divisor and places the result in a 32-bit register.
divweu	divweu RT, RA, RB	XO-form	Base	Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.
divwu	divwu RT, RA, RB	XO-form	Base	Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).
dmul	dmul FRT,FRA,FRB dmul. FRT,FRA,FRB	X-form	Decimal Floating-Point	Multiplies the contents of two DFP registers and places the result in another DFP register.
dmulq	dmulq vD, vA, vB	X-form	Decimal Floating-Point	Multiplies two 128-bit DFP numbers.
doze	doze	X-form	Privileged	Enters Doze power-saving mode (Supervisor only).
dqua	dqua FRT,FRA,FRB,RMC dqua. FRT,FRA,FRB,RMC	X-form	Decimal Floating-Point	Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.
dquai	dquai TE,FRT,FRB,RMC dquai. TE,FRT,FRB,RMC	Z23-form	Decimal Floating-Point	Adjusts the value to a form having the specified exponent in the range -16 to 15.
dquai.	dquai. FRT,FRB,UI	Z23-form	Decimal Floating-Point	Quantizes a DFP value to an immediate number of decimal digits.
dquaq	dquaq vD, vA, vB	X-form	Decimal Floating-Point	Adjusts exponent of 128-bit DFP number.
drdpq	drdpq FRT, vB	X-form	Decimal Floating-Point	Rounds DFP Quad (128-bit) to DFP Long (64-bit).
drintn	drintn R,FRT,FRB,RMC drintn. R,FRT,FRB,RMC	Z23-form	Decimal Floating-Point	Rounds a decimal floating-point number to an integer without recognizing an inexact exception.
drintx	drintx R,FRT,FRB,RMC drintx. R,FRT,FRB,RMC	Z23-form	Decimal Floating-Point	Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.
drrnd	drrnd FRT,FRA,FRB,RMC drrnd. FRT,FRA,FRB,RMC	Z23-form	Decimal Floating-Point	Rounds a decimal floating-point value to the specified number of significant digits.
drrnd.	drrnd. RA, RB	Z23-form	Decimal Floating-Point	Rerounds a decimal floating-point number to the specified precision.
drrndq	drrndq vD, vA, vB	X-form	Decimal Floating-Point	Rerounds a 128-bit DFP number to fewer digits.
drsp	drsp FRT,FRB drsp. FRT,FRB	X-form	Decimal Floating-Point	Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).
dscli	dscli FRT,FRA,SH (Rc=0)	Z23-form	Decimal Floating-Point	Shifts the significand of a DFP operand left by a specified number of digits.
dsri	dsri FRT, FRA, SH	Z23-form	Decimal Floating-Point	Shifts the coefficient of a DFP number right.
dss	dss STRM	X-form	Base	Stops a data stream prefetch operation.
dssall	dssall	X-form	Base	Stops all active data stream prefetch operations.
dst	dst RA, RB, STRM	X-form	Base	Initiates a hardware data stream prefetch (AltiVec Legacy).
dstst	dstst RA, RB, STRM	X-form	Base	Initiates a prefetch for writing.
dststt	dststt RA, RB, STRM	X-form	Base	Initiates a transient prefetch for writing.
dstt	dstt RA, RB, STRM	X-form	Base	Initiates a transient (non-temporal) data stream prefetch.
dsub	dsub FRT,FRA,FRB (Rc=0)	X-form	Decimal Floating-Point	Subtracts the contents of two DFP registers and places the result in another DFP register.
dsubq	dsubq vD, vA, vB	X-form	Decimal Floating-Point	Subtracts two 128-bit DFP numbers.
dtstdc	dtstdc BF,FRA,DCM	Z22-form	Decimal Floating-Point	Tests the data class of a DFP operand and sets the CR field.
dtstex	dtstex BF,FRA,FRB	X-form	Decimal Floating-Point	Compares the exponent values of two DFP operands and updates CR field BF and FPCC.
dtstsf	dtstsf BF,FRA,FRB	X-form	Decimal Floating-Point	Tests the significance of a DFP value in FPR[FRB] against a reference significance.
dtstsfi	dtstsfi BF, U, FRB	X-form	Decimal Floating-Point	Tests the significance of a decimal floating-point value in FPR[FRB] against an immediate value UIM.
dtstsfiq	dtstsfiq BF, U, FRB	X-form	Decimal Floating-Point	Tests DFP Quad significance.
dxex	dxex FRT,FRB dxex. FRT,FRB	X-form	Decimal Floating-Point	Extracts the biased exponent of a DFP operand in FRB and places it into FRT.
dxexq	dxexq vD, vB	X-form	Decimal Floating-Point	Extracts exponent from 128-bit DFP.
eciwx	eciwx RT, RA, RB	X-form	Base	Loads a word from an external device using the EAR register.
ecowx	ecowx RS, RA, RB	X-form	Base	Stores a word to an external device using the EAR register.
ehpriv	ehpriv OC	X-form	Embedded	Enters embedded hypervisor privileged state.
eieio	eieio	X-form	Base	Ensures that load/store instructions preceding the EIEIO complete before those following it. Used for Memory-Mapped I/O synchronization.
eqv	eqv RA, RS, RB	X-form	Base	Bitwise Equivalence (XNOR). RA = ~(RS ^ RB).
extldi	extldi ra,rs,n,b (n > 0)	XO-form	Base	Extracts a field of n bits starting at bit position b in the source register, left justifies this field in the target register, and clears all other bits of the target register to 0.
extlwi	extlwi ra,rs,n,b (n > 0)	XO-form	Base	Extracts a specified number of bits from the source register, left-justifies them, and places them in the target register.
extsb	extsb RT,RS extsb. RT,RS	X-form	Base	Sign extends the low byte of a register to the full width.
extsh	extsh RA, RS	X-form	Base	Sign extends the low halfword.
extsw	extsw RT,RS extsw. RT,RS	X-form	Base	Sign extends the low word (32-bit) to 64 bits.
extswsli	extswsli RA,RS,SH	XS-form	Base	Sign-extends the low-order 32 bits of a register, shifts it left by SH bits, and places the result in another register.
fabs	fabs FRT, FRB	X-form	Floating-Point	Computes absolute value of a float.
fadd	fadd FRT,FRA,FRB fadd. FRT,FRA,FRB	A-form	Floating-Point	Adds the contents of two floating-point registers and places the result into another register.
fcfid	fcfid FRT,FRB fcfid. FRT,FRB	X-form	Floating-Point	Converts a signed doubleword integer to a double-precision floating-point number.
fcfids	fcfids FRT,FRB fcfids. FRT,FRB	X-form	Floating-Point	Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.
fcfidu	fcfidu FRT, FRB	X-form	Floating-Point	Converts 64-bit Unsigned Int to Double.
fcfidus	fcfidus FRT, FRB	X-form	Floating-Point	Converts 64-bit Unsigned Int to Single.
fcfidus.	fcfidus. FRT,FRB	X-form	Floating-Point	Converts an unsigned doubleword integer in a floating-point register to a single-precision floating-point number, rounding the result.
fcmpu	fcmpu BF, FRA, FRB	X-form	Floating-Point	Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.
fcpsgn	fcpsgn FRT, FRA, FRB	X-form	Floating-Point	Copies sign from FRB to FRA.
fcpsgn.	fcpsgn. FRT,FRB,FRA	X-form	Floating-Point	Copies the sign of one floating-point number to another.
fctid	fctid FRT, FRB	X-form	Floating-Point	Converts a double-precision floating-point value to a signed 64-bit integer using rounding.
fctidu	fctidu FRT,FRB	X-form	Floating-Point	Converts a double-precision floating-point value to an unsigned 64-bit integer using rounding.
fctidz	fctidz FRT, FRB	X-form	Floating-Point	Converts Double to 64-bit Int (Truncate).
fctiw	fctiw FRT,FRB fctiw. FRT,FRB	X-form	Floating-Point	Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.
fctiwu	fctiwu FRT,FRB	X-form	Floating-Point	Converts a double-precision floating-point value to an unsigned integer using rounding.
fctiwuz	fctiwuz[.] FRT,FRB	X-form	Floating-Point	Converts a double-precision floating-point number to an unsigned integer word.
fctiwz	fctiwz FRT, FRB	X-form	Floating-Point	Converts Double to 32-bit Int (Truncate).
fdiv.	fdiv. FC,FA,FB	XO-form	Floating-Point	Divides the contents of two floating-point registers and updates the condition register.
fdivs	fdivs FRT,FRA,FRB	XO-form	Floating-Point	Divides the contents of two single precision floating point registers.
fmadd	fmadd FRT,FRA,FRC,FRB fmadd. FRT,FRA,FRC,FRB	A-form	Floating-Point	Performs (A * C) + B with a single rounding step. (The classic FMA).
fmr	fmr FRT,FRB fmr. FRT,FRB	X-form	Floating-Point	Copies a float register (Pseudo: for FRB).
fmrgew	fmrgew FRT,FRA,FRB	X-form	Floating-Point	Merges the even words from two floating-point registers into a third.
fmsub	fmsub FRT, FRA, FRC, FRB	A-form	Floating-Point	Multiplies two floating-point values and subtracts a third.
fmul	fmul FRT,FRA,FRC fmul. FRT,FRA,FRC	A-form	Floating-Point	Multiplies the contents of two floating-point registers and places the result into another register.
fnabs	fnabs FRT, FRB	X-form	Floating-Point	Computes negative absolute value of a float.
fneg	fneg FRT, FRB	X-form	Floating-Point	Negates a float.
fnmadd	fnmadd FRT,FRA,FRC,FRB fnmadd. FRT,FRA,FRC,FRB	A-form	Floating-Point	Performs a floating-point negative multiply-add operation.
fnmsub	fnmsub FRT, FRA, FRC, FRB	A-form	Floating-Point	-(A*C - B)
fre	fre FRT,FRB fre. FRT,FRB	A-form	Floating-Point	Estimates the reciprocal of a floating-point operand.
fre.	fre. RT,RA	XO-form	Floating-Point	Estimates the reciprocal of a floating-point number.
fres	fres FRT, FRB	A-form	Floating-Point	Estimates the reciprocal of a single-precision floating-point number.
frin	frin FRT,FRB frin. FRT,FRB	X-form	Floating-Point	Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.
frip	frip FRT,FRB frip. FRT,FRB	X-form	Floating-Point	Rounds a floating-point operand towards +infinity and places the result into a register.
frsp	frsp FRT,FRB frsp. FRT,FRB	X-form	Floating-Point	Rounds the contents of a floating-point register to single-precision.
frsqrte	frsqrte FRT,FRB frsqrte. FRT,FRB	A-form	Floating-Point	Estimates the reciprocal of the square root of a floating-point operand.
frsqrtes	frsqrtes FRT, FRB	A-form	Floating-Point	Estimates 1/sqrt(x) (Single Precision).
fsel	fsel FRT,FRA,FRC,FRB fsel. FRT,FRA,FRC,FRB	A-form	Floating-Point	Selects FRA if FRC >= 0, else FRB (Optional).
fsqrt	fsqrt FRT,FRB fsqrt. FRT,FRB	X-form	Floating-Point	Computes the square root of a floating-point number.
fsqrts	fsqrts FRT, FRB	X-form	Floating-Point	Computes square root (Single).
ftdiv	ftdiv BF, FRA, FRB	X-form	Floating-Point	Tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions.
ftsqrt	ftsqrt BF, FRB	X-form	Floating-Point	Tests for conditions that would cause a sqrt exception.
hashchk	hashchk RA	X-form	Base	Checks the hash of the Return Address Stack (ROP Protection).
hashchkp	hashchkp RA	X-form	Privileged	Checks the hash value of a memory location against a computed hash.
hashst	hashst RA	X-form	Base	Stores the computed doubleword hash value to a doubleword storage location.
hashstp	hashstp RA	X-form	Privileged	Privileged version of hash store.
hrfid	hrfid	XL-form	Privileged	Returns from a hypervisor interrupt.
icbi	icbi RA, RB	X-form	Base	Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.
icblc	icblc CT, RA, RB	X-form	Embedded	Clears an instruction cache line lock.
icbt	icbt RA, RB	X-form	Base	Provides a hint that the program will soon execute code from the block containing the byte addressed by EA, and that the block should be loaded into the cache specified by the CT field.
icbtls	icbtls CT, RA, RB	X-form	Privileged	Locks an instruction cache line.
iccci	iccci RA, RB	X-form	Embedded	Invalidates a congruence class in the instruction cache (Embedded).
icread	icread RA, RB	X-form	Embedded	Reads an instruction cache tag or data (Debug).
isel	isel RT, RA, RB, BC	A-form	Base	Conditionally copies RA or RB to RT based on a CR bit. (Equivalent to C ternary operator 'cond ? a : b').
isync	isync	XL-form	Base	Ensures that all instructions preceding the isync instruction have completed before it completes, and that no subsequent instructions are initiated until after the isync instruction completes.
lbarx	lbarx RT,RA,RB,EH lbarx RT,RA,RB	X-form	Base	Loads a byte from memory and reserves the location for exclusive access.
lbz	lbz RT, D(RA)	D-form	Base	Loads a byte from memory into the low 8 bits of a register and clears the upper 56 bits.
lbzbrx	lbzbrx RT,RA,RB	X-form	Base	Loads a byte from memory and reverses its order, placing it into a register.
lbzci	lbzci RT, RA, RB	X-form	Base	Loads a byte bypassing the cache. Used for memory-mapped I/O.
lbzcix	lbzcix RT,RA,RB	X-form	Base	Loads a byte from memory into a register, zeroing the upper bits of the target register.
lbzepx	lbzepx RT, RA, RB	X-form	Embedded	Loads a byte using the External PID (for OS kernels accessing user memory).
lbzu	lbzu RT,D(RA)	D-form	Base	Loads a byte from memory into a register, zeroing the upper bits of the target register, and updates the base address register.
lbzux	lbzux RT,RA,RB	X-form	Base	Loads a byte from memory into a register, zero-extends it to 32 bits, and updates the base address.
ld	ld RT, DS(RA)	DS-form	Base	Loads a doubleword (64 bits) from memory.
ldarx	ldarx RT,RA,RB,EH ldarx RT,RA,RB	X-form	Base	Loads a doubleword and creates a reservation. 64-bit version of lwarx.
ldat	ldat RT,RA,RB	X-form	Base	Atomically loads a doubleword from memory.
ldbrx	ldbrx RT, RA, RB	X-form	Base	Loads a doubleword from memory, byte-reversing it before storing in the target register.
ldci	ldci RT, RA, RB	X-form	Base	Loads a doubleword bypassing the cache.
lfd	lfd FRT,D(RA)	D-form	Floating-Point	Loads a double-precision floating-point value from memory into a floating-point register.
lfdp	lfdp FRTp,disp(RA)	DS-form	Floating-Point	Loads a doubleword-pair from storage into an even-odd pair of FPRs.
lfdu	lfdu FRT,D(RA)	D-form	Floating-Point	Loads a doubleword from memory into a floating-point register and updates the base address register.
lfs	lfs FRT,D(RA)	D-form	Floating-Point	Loads a single-precision floating-point value from memory into a floating-point register and converts it to double precision.
lfsu	lfsu FRT,D(RA)	X-form	Floating-Point	Loads a floating-point single-precision operand from memory into a register and updates the base address.
lfsx	lfsx FT,RA,RB	X-form	Floating-Point	Loads a single-precision floating-point value from memory into a floating-point register.
lha	lha RT, D(RA)	D-form	Base	Loads a halfword (16 bits) from memory and sign-extends it to 64 bits.
lharx	lharx RT, RA, RB	X-form	Base	Atomic Load Halfword.
lhax	lhax RT,RA,RB	X-form	Base	Loads a halfword from memory into a register and extends it to a full word, with indexed addressing.
lhbrx	lhbrx RT, RA, RB	X-form	Base	Loads a halfword from memory, byte-reverses it, and stores it in a register.
lhz	lhz RT, D(RA)	D-form	Base	Loads a halfword (16 bits) from memory and clears the upper 48 bits.
lhzci	lhzci RT, RA, RB	X-form	Base	Loads a halfword bypassing the cache.
lhzepx	lhzepx RT, RA, RB	X-form	Embedded	Loads a halfword using the External PID.
lhzu	lhzu RT,D(RA)	D-form	Base	Loads a halfword from memory into a register, zero-extends it to 64 bits, and updates the base address.
li	li RT, SIM	D-form	Base	Loads a 16-bit signed immediate into a register. (Alias for 'addi RT, 0, SIM').
lis	lis RT, SIM	D-form	Base	Loads a 16-bit immediate into the upper half of a 32-bit word. (Alias for 'addis RT, 0, SIM').
lmw	lmw RT, D(RA)	D-form	Base	Loads words from memory into registers RT through R31 (Context Switch).
lq	lq RTp, DQ(RA)	DQ-form	Base	Loads 128 bits into two adjacent GPRs (Even/Odd pair).
lqarx	lqarx RTp, RA, RB	X-form	Base	Loads a quadword from memory and reserves the location for conditional store.
lswi	lswi RT, RA, NB	X-form	Base	Loads a sequence of bytes from memory into general-purpose registers.
lswx	lswx RT, RA, RB	X-form	Base	Loads N bytes from memory (N in XER).
lvebx	lvebx VRT,RA,RB	X-form	VMX (AltiVec)	Loads a byte from memory into a vector register element.
lvehx	lvehx VX,RA,RB	X-form	VMX (AltiVec)	Loads a halfword element from memory into the corresponding halfword element of a vector register, with the address computed as the sum of RA and RB, aligned to a halfword boundary.
lvewx	lvewx VRT,RA,RB	X-form	VMX (AltiVec)	Loads a word from memory into a vector register element.
lvsl	lvsl VRT,RA,RB	X-form	VMX (AltiVec)	Loads a vector pattern suitable for shifting left indexed.
lvx	lvx vD, RA, RB	X-form	VMX (AltiVec)	Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).
lwa	lwa RT, DS(RA)	DS-form	Base	Loads a word (32 bits) from memory and sign-extends it to 64 bits.
lwarx	lwarx RT,RA,D lwarx EH=0 RT,RA,D lwarx EH=1 RT,RA,D	X-form	Base	Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).
lwat	lwat RT,RA,FC	X-form	Base	Loads a word from memory atomically.
lwax	lwax RT,RA,RB	X-form	Base	Loads a word from memory into a register using an indexed address.
lwbrx	lwbrx RT, RA, RB	X-form	Base	Loads a word and swaps bytes.
lwdi	lwdi RT, RA, RB	X-form	Embedded	Loads a word and sends decoration sideband signals to the bus.
lwsync	lwsync	Pseudo	Base	Orders loads with loads, stores with stores, and loads with stores. Does NOT order stores with loads. (Encoded as sync 1).
lwz	lwz RT, D(RA)	D-form	Base	Loads a word (32 bits) from memory and clears the upper 32 bits.
lwzci	lwzci RT, RA, RB	X-form	Base	Loads a word bypassing the cache.
lwzepx	lwzepx RT, RA, RB	X-form	Embedded	Loads a word using the External PID.
lxsd	lxsd VRT,disp(RA)	DS-form	VSX	Loads a doubleword from memory into a VSX scalar register.
lxsdx	lxsdx XT,RA,RB	X-form	VSX	Loads a doubleword from memory into a VSX scalar register.
lxsibzx	lxsibzx XT,RA,RB	X-form	VSX	Loads a byte from memory and places it into the specified VSX register, zeroing the upper half.
lxsiwax	lxsiwax XT, RA, RB	XX1-form	VSX	Loads a word from memory into the left-most doubleword element of a VSR, sign-extends it to 64 bits, and aligns it.
lxsiwzx	lxsiwzx XT, RA, RB	XX1-form	VSX	Loads a word from memory and places it into the specified VSX register, zero-extending it.
lxssp	lxssp RT,RA,RB	XX2-form	VSX	Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.
lxsspx	lxsspx XT,RA,RB	X-form	VSX	Loads a single-precision floating-point value from memory and converts it to double-precision format in a VSX register.
lxv	lxv XT, DQ(RA)	DQ-form	VSX	Loads a 128-bit vector from memory (VSX aligned offset).
lxvb16x	lxvb16x XT,RA,RB	X-form	VSX	Loads a vector of 16 byte elements from memory into a VSX register.
lxvd2x	lxvd2x XT, RA, RB	XX1-form	VSX	Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).
lxvdsx	lxvdsx XT, RA, RB	X-form	VSX	Loads a doubleword from memory and splats it into two elements of a VSX vector register.
lxvh8x	lxvh8x XT,RA,RB	X-form	VSX	Loads a vector of 8 halfwords from memory into a VSX register.
lxvkq	lxvkq XT,UIM	X-form	VSX	Loads a special value into a VSX vector register.
lxvl	lxvl XT, RA, RB	XX1-form	VSX	Loads N bytes into a vector, where N is specified in a GPR.
lxvll	lxvll XT,RA,RB	X-form	VSX	Loads a variable-length vector from memory into a VSX register, left-justifying the data.
lxvp	lxvp XT, DQ(RA)	DQ-form	VSX	Loads a double quadword from memory into two VSX registers.
lxvpx	lxvpx XTp,RA,RB	X-form	VSX	Loads a vector from memory into two VSR registers.
lxvrbx	lxvrbx XT,RA,RB	X-form	VSX	Loads a byte from memory into the rightmost byte of a VSX vector register.
lxvrdx	lxvrdx XT,RA,RB	X-form	VSX	Loads a doubleword from memory into the rightmost element of a VSX vector register.
lxvrhx	lxvrhx XT,RA,RB	X-form	VSX	Loads a halfword from memory into the rightmost element of a VSX vector register.
lxvrwx	lxvrwx XT,RA,RB	X-form	VSX	Loads a word from memory into the rightmost word of a VSX vector register.
lxvw4x	lxvw4x XT, RA, RB	XX1-form	VSX	Loads four words into a vector (unaligned).
lxvwsx	lxvwsx XT, RA, RB	XX1-form	VSX	Loads a 32-bit word and replicates it across the vector.
lxvx	lxvx XT,RA,RB	X-form	VSX	Loads a quadword from memory into a VSX register.
macchw	macchw RT, RA, RB	XO-form	Embedded	Multiply bottom half of RA by top half of RB, add to RT.
macchws	macchws RT, RA, RB	XO-form	Embedded	Signed Multiply Accumulate Cross Halfword with Saturation.
macchwsu	macchwsu RT, RA, RB	XO-form	Embedded	Mixed Sign Multiply Accumulate Cross Halfword with Saturation.
macchwu	macchwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply Accumulate Cross Halfword.
machhw	machhw RT, RA, RB	XO-form	Embedded	Multiply top half of RA by top half of RB, add to RT.
machhws	machhws RT, RA, RB	XO-form	Embedded	Signed Multiply Accumulate High Halfword with Saturation.
machhwsu	machhwsu RT, RA, RB	XO-form	Embedded	Mixed Sign Multiply Accumulate High Halfword with Saturation.
machhwu	machhwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply Accumulate High Halfword.
maclhw	maclhw RT, RA, RB	XO-form	Embedded	Multiply bottom half of RA by bottom half of RB, add to RT.
maclhws	maclhws RT, RA, RB	XO-form	Embedded	Signed Multiply Accumulate Low Halfword with Saturation.
maclhwsu	maclhwsu RT, RA, RB	XO-form	Embedded	Mixed Sign Multiply Accumulate Low Halfword with Saturation.
maclhwu	maclhwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply Accumulate Low Halfword.
maddhd	maddhd RT,RA,RB,RC	VA-form	Base	Multiplies two 64-bit operands and adds the result to a third 64-bit operand, placing the high-order 64 bits of the sum into a target register.
mbar	mbar MO	X-form	Embedded	Ensures memory access ordering (Embedded version of 'sync').
mcrf	mcrf BF, BFA	XL-form	Base	Copies the contents of one Condition Register field to another. Used to save comparison results.
mcrfs	mcrfs BF, BFA	X-form	Floating-Point	Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.
mcrxrx	mcrxrx BF	X-form	Base	Copies the contents of the XER register fields OV, OV32, CA, and CA32 to the specified condition register field.
mfbhrbe	mfbhrbe RT, BHRBE	X-form	Base	Reads a specific entry from the BHRB.
mfcr	mfcr RT	X-form	Base	Copies the entire 32-bit Condition Register into a General Purpose Register.
mfctr	mfctr RT	XFX-form	Base	Moves CTR to GPR. (Alias for 'mfspr RT, 9').
mfdcr	mfdcr RT, DCRN	XFX-form	Embedded	Reads an on-chip peripheral register (DCR).
mffs	mffs FRT mffs. FRT	X-form	Floating-Point	Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.
mffscdrn	mffscdrn FRT,FRB	X-form	Floating-Point	Moves control bits from FPSCR to a register and sets the DRN field.
mffsl	mffsl FRT	X-form	Floating-Point	Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.
mflr	mflr RT	XFX-form	Base	Moves LR to GPR. (Alias for 'mfspr RT, 8').
mfmsr	mfmsr RT	X-form	Privileged	Moves the contents of the Machine State Register (MSR) into a general-purpose register.
mfocrf	mfocrf RT, FXM	XFX-form	Base	Moves a single CR field to a GPR.
mfpmr	mfpmr RT, PMRN	X-form	Embedded	Reads a performance monitor register (Embedded).
mfpvr	mfpvr RT	X-form	Privileged	Reads the PVR (Processor ID).
mfspr	mfspr RT, SPR	XFX-form	Base	Moves the contents of a special purpose register into a general-purpose register.
mfsr	mfsr RT, SR	X-form	Base	Legacy 32-bit segment register read.
mfsrin	mfsrin RT, RB	X-form	Base	Indirect read of segment register using RB.
mftar	mftar RT	XFX-form	Base	Reads the TAR into a GPR.
mftb	mftb RT,268 mftb RT	XFX-form	Base	Moves the contents of the Time Base Register (TBR) into a general-purpose register.
mftbu	mftbu RT	XFX-form	Base	Reads the upper 32 bits of the Timebase (32-bit implementations).
mfvsrd	mfvsrd RA, XS	XX1-form	VSX	Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).
mfvsrld	mfvsrld RA, XS	XX1-form	VSX	Moves the lower doubleword of a vector register to a general-purpose register.
mfvsrwz	mfvsrwz RA, XS	XX1-form	VSX	Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.
modsd	modsd RT, RA, RB	X-form	Base	Calculates remainder of signed doubleword division.
modsq	modsq vD, vA, vB	VX-form	Base	Computes remainder of 128-bit signed division.
modsw	modsw RT, RA, RB	X-form	Base	Calculates remainder of signed word division.
modud	modud RT, RA, RB	X-form	Base	Calculates remainder of unsigned doubleword division.
moduq	moduq vD, vA, vB	VX-form	Base	Computes remainder of 128-bit unsigned division.
moduw	moduw RT, RA, RB	X-form	Base	Calculates remainder of unsigned word division.
mr	mr RA, RS	X-form	Base	Copies contents of RS to RA. (Alias for 'or RA, RS, RS').
msgclr	msgclr RB	X-form	Privileged	Clears a pending doorbell interrupt (Inter-processor comms).
msgclrp	msgclrp RB	X-form	Privileged	Clears a privileged doorbell interrupt.
msgslp	msgslp RB	X-form	Privileged	Transitions the processor to a sleep state via message.
msgsnd	msgsnd RB	X-form	Privileged	Sends a doorbell interrupt to another processor.
msgsndp	msgsndp RB	X-form	Privileged	Sends a message to other threads on the same processor or sub-processor.
msgsndu	msgsndu RB	X-form	Privileged	Sends a message to other threads in the system.
msgsync	msgsync	X-form	Privileged	Provides an ordering function for stores relative to data accesses by other threads after a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt.
msync	msync	X-form	Embedded	Synchronizes memory accesses (Alias for sync).
mtcrf	mtcrf FXM, RS	XFX-form	Base	Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).
mtctr	mtctr RS	XFX-form	Base	Moves GPR to CTR. (Alias for 'mtspr 9, RS').
mtdcr	mtdcr DCRN, RS	XFX-form	Embedded	Writes an on-chip peripheral register (DCR).
mtfsb0	mtfsb0 BT	X-form	Floating-Point	Clears a specific bit in the FPSCR.
mtfsb1	mtfsb1 BT	X-form	Floating-Point	Sets a specific bit in the FPSCR.
mtfsf	mtfsf FLM,FRB,L,W mtfsf. FLM,FRB,L,W	XFL-form	Floating-Point	Moves the contents of a floating-point register into specified fields of the FPSCR.
mtfsfi	mtfsfi BF, U	X-form	Floating-Point	Writes a 4-bit immediate to a specific FPSCR field.
mtlr	mtlr RS	XFX-form	Base	Moves GPR to LR. (Alias for 'mtspr 8, RS').
mtmsr	mtmsr RS,L mtmsr RS	X-form	Privileged	Sets the Machine State Register (MSR) based on the contents of a source register and a control bit.
mtmsrd	mtmsrd RS,L mtmsrd RS	X-form	Privileged	Sets the Machine State Register (MSR) based on the contents of a source register and an L field.
mtocrf	mtocrf FXM, RS	XFX-form	Base	Moves a GPR field to a single CR field.
mtpmr	mtpmr PMRN, RS	X-form	Embedded	Writes a performance monitor register (Embedded).
mtspr	mtspr SPR, RS	XFX-form	Base	Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).
mtsr	mtsr SR, RS	X-form	Base	Legacy 32-bit segment register write.
mtsrin	mtsrin RS, RB	X-form	Base	Indirect write of segment register using RB.
mttar	mttar RS	XFX-form	Base	Moves a GPR value to the TAR.
mtvscr	mtvscr VRB	VX-form	VMX (AltiVec)	Moves the contents of a vector register word into the VSCR.
mtvsrbm	mtvsrbm VRT,RB	VX-form	VMX (AltiVec)	Moves a byte mask from a GPR to a VSR.
mtvsrbmi	N/A	XO-form	Base	Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.
mtvsrd	mtvsrd XT, RA	XX1-form	VSX	Moves 64 bits from a GPR to a VSR.
mtvsrdd	mtvsrdd XT, RA, RB	X-form	VSX	Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.
mtvsrqm	mtvsrqm VRT,RB	VX-form	VMX (AltiVec)	Moves a quadword mask from a general-purpose register to a vector scalar register.
mtvsrwa	mtvsrwa XT, RA	XX1-form	VSX	Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.
mtvsrwm	mtvsrwm VRT,RB	VX-form	VMX (AltiVec)	Moves a word mask from a general-purpose register to a vector scalar register.
mtvsrws	mtvsrws XT, RA	XX1-form	VSX	Moves a 32-bit word from a GPR and replicates it across the vector.
mulchw	mulchw RT, RA, RB	XO-form	Embedded	Multiply bottom half of RA by top half of RB.
mulchwu	mulchwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply Cross Halfword.
mulhd	mulhd RT, RA, RB	XO-form	Base	Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).
mulhd.	mulhd. RT,RA,RB	XO-form	Base	Multiplies the contents of two registers and places the high-order 64 bits of the product into a target register.
mulhdu	mulhdu RT, RA, RB	XO-form	Base	Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).
mulhhw	mulhhw RT, RA, RB	XO-form	Embedded	Multiply top half of RA by top half of RB.
mulhhwu	mulhhwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply High Halfword.
mulhw	mulhw RT, RA, RB	XO-form	Base	Multiplies two 32-bit integers and returns the upper 32 bits (Signed).
mulhwu	mulhwu RT, RA, RB	XO-form	Base	Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).
mulld	mulld RT,RA,RB mulldo RT,RA,RB	XO-form	Base	Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.
mullhw	mullhw RT, RA, RB	XO-form	Embedded	Multiply bottom half of RA by bottom half of RB.
mullhwu	mullhwu RT, RA, RB	XO-form	Embedded	Unsigned Multiply Low Halfword.
mulli	mulli RT,RA,SI	D-form	Base	Multiplies the contents of a register by an immediate value and places the low-order 32 bits of the product into another register.
mullw	mullw RT, RA, RB	XO-form	Base	Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.
nand	nand RA, RS, RB	X-form	Base	Bitwise NAND. RA = ~(RS & RB).
nap	nap	X-form	Privileged	Enters Nap power-saving mode (Supervisor only).
neg	neg RT, RA	XO-form	Base	Computes the two's complement negation of a register (0 - RT).
nmacchw	nmacchw RT, RA, RB	XO-form	Embedded	Negate product of cross halfwords and add to accumulator.
nmacchws	nmacchws RT, RA, RB	XO-form	Embedded	Negate product of cross halfwords and add to accumulator (Signed Saturation).
nmachhw	nmachhw RT, RA, RB	XO-form	Embedded	Negate product of high halfwords and add to accumulator.
nmachhws	nmachhws RT, RA, RB	XO-form	Embedded	Negate product of high halfwords and add to accumulator (Signed Saturation).
nmaclhw	nmaclhw RT, RA, RB	XO-form	Embedded	Negate product of low halfwords and add to accumulator.
nmaclhws	nmaclhws RT, RA, RB	XO-form	Embedded	Negate product of low halfwords and add to accumulator (Signed Saturation).
nop	nop	D-form	Base	Does nothing. (Alias for 'ori 0, 0, 0').
nor	nor RA, RS, RB	X-form	Base	Bitwise NOR. RA = ~(RS \| RB).
not	not Rx,Ry not. Rx,Ry	X-form	Base	Complements the contents of one register and places the result into another register.
or	or RT,RA,RB miso	X-form	Base	Performs a bitwise OR operation on the contents of two registers and places the result in a third register.
or.	or. RT,RA,RB	X-form	Base	Performs a bitwise OR operation on the contents of two registers and updates the condition register.
orc	orc RA,RS,RB orc. RA,RS,RB	X-form	Base	Performs a bitwise OR operation between the contents of two registers and the complement of the third register.
ori	ori RT,RS,SImm ori R31,R31,0	D-form	Base	Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.
oris	oris RA, RS, UI	D-form	Base	Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.
paddi	paddi RT, RA, SI, R	MLS:D-form	Prefixed	Adds 34-bit immediate.
paste	paste RA, RB	X-form	Privileged	Transfers data from the copy buffer to a specified memory location.
paste.	paste. RA, RB	X-form	Privileged	Paste operation that updates CR0 to indicate success/fail.
pdepd	pdepd RA, RS, RB	X-form	Base	Deposits bits from RS to RA under control of mask RB (Scalar).
pextd	pextd RA, RS, RB	X-form	Base	Extracts bits from a source register based on a mask and places them into the target register.
pla	pla RT, label	Pseudo	Prefixed	Pseudo-instruction for paddi with R=1. Loads the address of a label.
plbz	plbz RT, D34(RA), R	MLS:D-form	Prefixed	Loads a byte and zero-extends it, using a 34-bit offset.
pld	pld RT, D34(RA), R	MLS:D-form	Prefixed	Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).
plfd	plfd RT,RA,RB	D-form	Prefixed	Loads a double-precision floating-point value from memory into a VSX register.
plh	plh RT, D(RA), R	MLS:D-form	Prefixed	Loads 16-bit halfword using 34-bit offset.
plha	plha RT, D(RA), R	MLS:D-form	Prefixed	Loads 16-bit halfword (Sign Extended) using 34-bit offset.
pli	pli RT, SI34	MLS:D-form	Prefixed	Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).
plq	plq RTp, D(RA), R	MLS:D-form	Prefixed	Loads 128 bits into two GPRs using a 34-bit offset.
plwa	plwa RT, D(RA), R	MLS:D-form	Prefixed	Loads 32-bit word (Sign Extended) using 34-bit offset.
plwz	plwz RT, D34(RA), R	MLS:D-form	Prefixed	Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.
plxv	plxv RT,RA,RB	D-form	Prefixed	Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.
plxvp	plxvp XT, D(RA), R	8LS:D-form	Prefixed	Loads a 256-bit vector pair with 34-bit offset.
pmxvbf16ger2	pmxvbf16ger2 AT, XA, XB, XMSK, YMSK	MMIRR-form	Prefixed	Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.
pmxvbf16ger2np	pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK	MMIRR:XX3-form	VSX	Performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation.
pmxvf16ger2np	pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK	MMIRR:XX3-form	VSX	Performs a masked vector operation with negative multiplication and positive accumulation.
pmxvf16ger2pp	pmxvf16ger2pp	MMIRR:XX3-form	MMA	Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.
pmxvf32gernp	pmxvf32gernp AT,XA,XB,XMSK,YMSK	MMIRR:XX3-form	VSX	Performs a masked vector operation with negative multiplication and positive accumulation.
pmxvf32gerpp	pmxvf32gerpp	MMIRR:XX3-form	MMA	Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.
pmxvf64ger	pmxvf64ger AT, XA, XB, XMSK, YMSK	MMIRR-form	Prefixed	Masked version of Double-Precision MMA.
pmxvf64gernn	pmxvf64gernn	MMIRR:XX3-form	MMA	Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.
pmxvf64gernp	pmxvf64gernp AT,XAp,XB,XMSK,YMSK	MMIRR:XX3-form	VSX	Performs a masked vector floating-point operation with negative multiplication and positive accumulation.
pmxvi4ger8	pmxvi4ger8 AT, XA, XB, XMSK, YMSK	MMIRR-form	Prefixed	Masked 4-bit integer matrix multiply.
pmxvi4ger8pp	pmxvi4ger8pp AT, XA, XB, XMSK, YMSK	MMIRR-form	Prefixed	Masked unsigned 4-bit integer matrix multiply.
pmxvi8ger4	pmxvi8ger4 AT, XA, XB, XMSK, YMSK	MMIRR-form	Prefixed	Masked version of 8-bit integer MMA.
pmxvi8ger4pp	pmxvi8ger4pp	MMIRR:XX3-form	MMA	Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.
pnop	pnop	*-form	Prefixed	No operation is performed.
popcntb	popcntb RA,RS	X-form	Base	Counts the number of one bits in each byte of a register.
popcntd	popcntd RA, RS	X-form	Base	Counts the number of set bits (1s) in a 64-bit register.
popcntw	popcntw RA, RS	X-form	Base	Counts the number of set bits (1s) in the lower 32 bits of a register.
prtyd	prtyd RA, RS	X-form	Base	Calculates parity of a doubleword (Scalar).
prtyw	prtyw RA, RS	X-form	Base	Calculates parity of a word (Scalar).
ps_add	ps_add FRT, FRA, FRB	A-form	VMX (AltiVec)	Adds two paired singles.
ps_madd	ps_madd FRT, FRA, FRC, FRB	A-form	VMX (AltiVec)	Multiply-Add on paired singles.
ps_mul	ps_mul FRT, FRA, FRC	A-form	VMX (AltiVec)	Multiplies two paired singles.
ps_sub	ps_sub FRT, FRA, FRB	A-form	VMX (AltiVec)	Subtracts two paired singles.
psq_l	psq_l FRT, D(RA), W, I	X-form	VMX (AltiVec)	Loads a paired single from memory (Embedded/Legacy).
psq_st	psq_st FRS, D(RA), W, I	X-form	VMX (AltiVec)	Stores a paired single to memory (Embedded/Legacy).
pstb	pstb RS, D(RA), R	MLS:D-form	Prefixed	Stores byte using 34-bit offset.
pstfd	pstfd FRT,RA,RB	MLS:D-form	Prefixed	Stores a double-precision floating-point value from a register to memory.
pstfs	pstfs FRT,RA,RB	MLS:D-form	Floating-Point	Stores a single-precision floating-point value from a register to memory.
psth	psth RS, D(RA), R	MLS:D-form	Prefixed	Stores halfword using 34-bit offset.
pstq	pstq RSp, D(RA), R	MLS:D-form	Prefixed	Stores 128 bits from two GPRs using a 34-bit offset.
pststd	pststd RS, D34(RA), R	MLS:D-form	Prefixed	Stores a 64-bit value to memory using a 34-bit immediate offset.
pstw	pstw RS, D(RA), R	MLS:D-form	Prefixed	Stores word using 34-bit offset.
pstxvp	pstxvp XS, D(RA), R	8LS:D-form	Prefixed	Stores a 256-bit vector pair with 34-bit offset.
rfebb	rfebb S rfebb	XL-form	Base	Returns control to the address specified by EBBRR0:61 \|\| 0b00 or 320 \|\| EBBRR32:61 \|\| 0b00, depending on MSRSF.
rfid	rfid	XL-form	Privileged	Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.
rfscv	rfscv	XL-form	Privileged	Returns from a vectored system call.
ripv	ripv	X-form	Privileged	Enters Deep Sleep mode (Supervisor only).
rldcr	rldcr RT,RS,RB,ME rldcr. RT,RS,RB,ME	MDS-form	Base	Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.
rldic	rldic RT,RA,RB,MB rldic. RT,RA,RB,MB	MD-form	Base	Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.
rldicl	rldicl RA, RS, SH, MB	MD-form	Base	Rotates the contents of a register left by a specified number of bits and clears higher-order bits.
rldicr	rldicr RA, RS, SH, ME	MD-form	Base	Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).
rldimi	rldimi RA, RS, SH, MB	MD-form	Base	Rotates 64-bit value and inserts into target under mask.
rlwimi	rlwimi RA, RS, SH, MB, ME	M-form	Base	Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.
rlwinm	rlwinm RA,RS,SH,MB,ME rlwinm. RA,RS,SH,MB,ME	M-form	Base	Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.
rlwnm	rlwnm RT,RS,RB,MB,ME rlwnm. RT,RS,RB,MB,ME	M-form	Base	Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.
rotatel	rotatel RT,RA,RB	XO-form	Base	Rotates the contents of a register to the left by a specified number of bit positions.
sc	sc LEV	SC-form	Base	Provides the means by which a program can call upon the system to perform a service.
scv	scv LEV	SC-form	Base	Performs a system call to a fixed vector address (Faster than 'sc').
setb	setb RT, BFA	X-form	Base	Sets the target register based on the condition register field BFA.
setbc	setbc RT, BI	X-form	Base	Sets RT to 1 if CR bit is set, else 0. (Branchless logic).
setbcr	setbcr RT, BI	X-form	Base	Sets RT to 1 if CR bit is clear, else 0.
setnbc	setnbc RT, BI	X-form	Base	Sets RT to -1 if CR bit is set, else 0.
setnbcr	setnbcr RT, BI	X-form	Base	Sets RT to -1 if CR bit is clear, else 0.
slbfee.	slbfee. RT,RB	X-form	Base	Searches the SLB for an entry that matches the effective address specified by register RB.
slbia	slbia slbia IH	X-form	Privileged	Invalidates all Segment Lookaside Buffer entries (OS Management).
slbiag	slbiag RS,L slbiag RS	X-form	Base	Invalidates all SLBs for a specified LPID and PID.
slbie	slbie RB	X-form	Privileged	Invalidates an SLB entry. Critical for memory management on Power systems.
slbieg	slbieg RS,RB	X-form	Base	Invalidates SLB entries based on the contents of registers RS and RB.
slbmfee	slbmfee RT, RB	X-form	Privileged	Reads the ESID part of an SLB entry.
slbmfev	slbmfev RT, RB	X-form	Privileged	Reads software-loaded SLB entries and places the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields into register RT.
slbmte	slbmte RS, RB	X-form	Privileged	Writes an SLB entry (Mapping effective to virtual address).
slbsync	slbsync	X-form	Privileged	Provides an ordering function for the effects of all slbieg and slbiag instructions executed by the thread executing the slbsync instruction.
sld	sld RA, RS, RB	X-form	Base	Shifts a 64-bit register left by the amount specified in RB.
sleep	sleep	X-form	Privileged	Enters Sleep power-saving mode (Supervisor only).
slw	slw RT,RA,RB slw. RT,RA,RB	X-form	Base	Shifts a 32-bit register left by the amount specified in RB.
slw.	slw. RT,RA,RB	XO-form	Base	Shifts the contents of a register left by a specified number of bits and updates the condition register.
srad	srad RA, RS, RB	X-form	Base	Arithmetic right shift of 64-bit value (preserves sign).
srad.	srad. RT,RA,RB	X-form	Base	Shifts the contents of a doubleword register right algebraically, shifting in sign bits.
sradi	sradi RA, RS, SH	XS-form	Base	Performs an arithmetic right shift on a 64-bit doubleword by a constant amount.
sraw	sraw RA, RS, RB	X-form	Base	Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.
srawi	srawi RA, RS, SH	X-form	Base	Shifts the contents of a register right by an immediate value and replicates the sign bit.
srd	srd RA, RS, RB	X-form	Base	Logical right shift of 64-bit value.
srw	srw RA, RS, RB	X-form	Base	Performs a logical right shift (zeros shifted in) on a 32-bit word.
stax	stax RS,RA,RB	X-form	Base	Performs an atomic update to an aligned memory location based on the function code (FC) specified.
stb	stb RS, D(RA)	D-form	Base	Stores the low 8 bits of a register to memory.
stbci	stbci RS, RA, RB	X-form	Base	Stores a byte bypassing the cache.
stbcix	stbcix RS,RA,RB	X-form	Base	Stores a byte from a register to memory with caching inhibited and guarded.
stbcx.	stbcx. RS, RA, RB	X-form	Base	Stores a byte from a register to memory if the reservation is valid and matches the address.
stbepx	stbepx RS, RA, RB	X-form	Embedded	Stores a byte using the External PID.
std	std RS, DS(RA)	DS-form	Base	Stores a 64-bit doubleword to memory.
stdbrx	stdbrx RS, RA, RB	X-form	Base	Swaps bytes and stores 64 bits.
stdci	stdci RS, RA, RB	X-form	Base	Stores a doubleword bypassing the cache.
stdcx.	stdcx. RS, RA, RB	X-form	Base	Stores a doubleword from a register to memory if the reservation is valid and matches the address used for the reservation.
stdi	stdi RS, RA, RB	X-form	Embedded	Stores a word and sends decoration sideband signals.
stdu	stdu RS,disp(RA)	DS-form	Base	Stores a doubleword from a register to memory and updates the base address register.
stdx	stdx RS,RA,RB	X-form	Base	Stores a doubleword from a register to memory using an indexed address.
stfd	stfd FRS,D(RA)	D-form	Floating-Point	Stores a double-precision floating-point value from a register to memory.
stfdp	stfdp FRSp,disp(RA)	DS-form	Floating-Point	Stores the contents of two floating-point registers into memory as a doubleword pair.
stfdux	stfdux FRS,RA,RB	X-form	Floating-Point	Stores the contents of a floating-point register into memory and updates the base address register.
stfs	stfs FRS,D(RA)	DS-form	Floating-Point	Stores a single-precision floating-point value from an FPR to memory.
stfsx	stfsx FRS,RA,RB	X-form	Floating-Point	Stores a single-precision floating-point value from a register to memory using an indexed address.
sth	sth RS, D(RA)	D-form	Base	Stores the high half of a doubleword from a register to memory.
sthbrx	sthbrx RS, RA, RB	X-form	Base	Swaps bytes and stores a halfword.
sthci	sthci RS, RA, RB	X-form	Base	Stores a halfword bypassing the cache.
sthcix	sthcix RT,RB,RA	X-form	Base	Stores a halfword from a general-purpose register to memory, with caching inhibited.
sthcx.	sthcx. RS, RA, RB	X-form	Base	Stores a halfword from a register to memory conditionally based on a reservation.
sthep	sthepx RS, RA, RB	X-form	Embedded	Stores a halfword using the External PID.
stmw	stmw RT, D(RA)	D-form	Base	Stores words from registers RT through R31 to memory (Context Switch).
stop	stop	X-form	Privileged	Stops instruction execution and enters a power-saving state (replaces nap/doze on P9+).
stq	stq RSp, DQ(RA)	DQ-form	Base	Stores a quadword from two general-purpose registers into memory.
stqcx.	stqcx. RS, RA, RB	X-form	Base	Stores a quadword from a register to memory if a reservation exists and the conditions are met.
stswi	stswi RT, RA, NB	X-form	Base	Stores a string of words from general-purpose registers to memory, starting at the address in RA and using an immediate byte count.
stswx	stswx RT, RA, RB	X-form	Base	Stores N bytes to memory (N in XER).
stvebx	stvebx VRS,RA,RB	X-form	VMX (AltiVec)	Stores a byte element from a vector register into memory.
stvehx	stvehx VRS,RA,RB	X-form	VMX (AltiVec)	Stores a halfword element from a vector register to memory.
stvx	stvx vS, RA, RB	X-form	VMX (AltiVec)	Stores a quadword from a vector register to memory at an address formed by adding two general-purpose registers.
stvxl	stvxl VS,RA,RB	X-form	Base	Stores a vector element to memory, with the last element being stored if the index is out of bounds.
stw	stw RS, D(RA)	D-form	Base	Stores the low 32 bits of a register to memory.
stwat	stwat RS,RA,FC	X-form	Base	Stores a word atomically to memory.
stwbrx	stwbrx RS, RA, RB	X-form	Base	Swaps bytes and stores a word.
stwci	stwci RS, RA, RB	X-form	Base	Stores a word bypassing the cache.
stwcix	stwcix RS,RA,RB	X-form	Base	Stores a word from a source register to memory with caching inhibited.
stwcx.	stwcx. RS, RA, RB	X-form	Base	Stores a word from a register to memory if the reservation is valid and matches the address used in the corresponding lwarx instruction.
stwepx	stwepx RS, RA, RB	X-form	Embedded	Stores a word using the External PID.
stxsd	stxsd VRS,disp(RA)	DS-form	VSX	Stores the contents of doubleword element 0 of VSR[XS] to memory.
stxsdx	stxsdx XS,RA,RB	X-form	VSX	Stores a doubleword from a VSX scalar register to memory.
stxsibx	stxsibx XS,RA,RB	X-form	VSX	Stores a byte from a VSX scalar register into memory at an address formed by adding two general-purpose registers.
stxsiwx	stxsiwx XS, RA, RB	XX1-form	VSX	Stores a single-precision floating-point value from a VSX register into memory, indexed by another register.
stxssp	stxssp VRS,disp(RA)	DS-form	VSX	Stores a single-precision floating-point value from a VSX register to memory.
stxsspx	stxsspx XS,RA,RB	X-form	VSX	Stores a single-precision floating-point value from a VSX register to memory.
stxv	stxv XS, DQ(RA)	DQ-form	VSX	Stores a 128-bit vector to memory (VSX aligned offset).
stxvb16x	stxvb16x XS,RA,RB	X-form	VSX	Stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.
stxvd2x	stxvd2x XS, RA, RB	XX1-form	VSX	Stores a 128-bit VSX register to memory. Does NOT require alignment.
stxvh8x	stxvh8x XS,RA,RB	X-form	VSX	Stores a vector of 8 halfword elements from VSR[X] into memory using indexed addressing.
stxvl	stxvl XS, RA, RB	XX1-form	VSX	Stores a specified number of bytes from a VSX vector register to memory.
stxvll	stxvll XS,RA,RB	X-form	VSX	Stores a left-justified vector from a VSX register to memory.
stxvp	stxvp XS, DQ(RA)	DQ-form	VSX	Stores a pair of VSX vector registers to memory.
stxvpx	stxvpx XSp,RA,RB	X-form	VSX	Stores a vector from two VSR registers into memory at the effective address.
stxvrbx	stxvrbx XS,RA,RB	X-form	VSX	Stores the rightmost byte of a VSX vector element to memory.
stxvrdx	stxvrdx VX,RA,RB	X-form	VSX	Stores the rightmost doubleword of a VSX vector register to memory.
stxvrhx	stxvrhx XS,RA,RB	X-form	VSX	Stores the rightmost halfword of a VSX vector element to memory.
stxvw4x	stxvw4x XS, RA, RB	XX1-form	VSX	Stores four words from a vector (unaligned).
stxvx	stxvx xW,r0,rPW stxvx xX,r0,rPX stxvx xY,r0,rPY stxvx xZ,r0,rPZ	X-form	VSX	Stores a vector element from the VSX register file to memory.
subfc.	subfc. RT,RA,RB	XO-form	Base	Subtracts the contents of one register from the complement of another and updates the carry-out flag.
sync	sync sync L hwsync lwsync ptesync plwsync stncisync stcisync stsncisync stcisync	X-form	Base	Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.
tabort.	tabort. RA	X-form	Transactional Memory	Forces a transaction failure and rollback.
tabortdc	tabortdc TO, RA, RB	X-form	Transactional Memory	Aborts a transaction if the condition is met (Doubleword comparison).
tabortdci	tabortdci TO, RA, SI	X-form	Transactional Memory	Aborts transaction if doubleword condition (Immediate) is met.
tabortwc	tabortwc TO, RA, RB	X-form	Transactional Memory	Aborts a transaction if the condition is met (Word comparison).
tabortwci	tabortwci TO, RA, SI	X-form	Transactional Memory	Aborts transaction if word condition (Immediate) is met.
tbegin.	tbegin. R	X-form	Transactional Memory	Initiates a hardware transaction. If the transaction fails, execution rolls back to this point. Sets CR0 based on success/failure.
tcheck	tcheck BF	X-form	Transactional Memory	Checks transaction status and updates CR.
td	td TO, RA, RB	X-form	Base	Traps if condition (comparison of doublewords) is met.
tdi	tdi TO, RA, SIM	D-form	Base	Compares the contents of a register with an immediate value and invokes a trap handler if specified conditions are met.
tend.	tend. A	X-form	Transactional Memory	Commits the current hardware transaction. If successful, memory changes become visible atomically.
tlbia	tlbia	X-form	Privileged	Invalidates the entire Translation Lookaside Buffer.
tlbie	tlbie RB, RS	X-form	Privileged	Invalidates a TLB entry corresponding to the address in RB.
tlbiel	tlbiel RS, RIC, PRS, effR	X-form	Privileged	Invalidates a TLB entry on the current processor only.
tlbilx	tlbilx T, RA, RB	X-form	Embedded	Invalidates TLB entries on the local processor based on Process ID (PID).
tlbivax	tlbivax RA, RB	X-form	Embedded	Invalidates a TLB entry by virtual address.
tlbre	tlbre	X-form	Embedded	Reads a TLB entry into MAS registers.
tlbsx	tlbsx RA, RB	X-form	Embedded	Searches the TLB for an address.
tlbsync	tlbsync	X-form	Privileged	Provides an ordering function for the effects of all tlbie instructions executed by the thread executing the tlbsync instruction.
tlbwe	tlbwe	X-form	Embedded	Writes a TLB entry from MAS registers.
trap	trap	Pseudo	Base	Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).
trechkpt	trechkpt	X-form	Transactional Memory	Updates the transaction checkpoint.
tresume	tresume.	X-form	Transactional Memory	Resumes a suspended transaction.
tsr	tsr L	X-form	Transactional Memory	Suspends or resumes a transaction based on L.
tsuspend	tsuspend.	X-form	Transactional Memory	Suspends the current transaction.
tw	tw TO, RA, RB	X-form	Base	Traps if condition (comparison of words) is met.
twi	twi TO, RA, SIM	D-form	Base	Compares the contents of register RA with an immediate value and invokes the system trap handler if any specified condition is met.
urfid	urfid	XL-form	Privileged	Returns from an ultravisor interrupt.
vabsdub	vabsdub vD, vA, vB	VA-form	VMX (AltiVec)	Returns the absolute value of the difference of integer values in byte elements.
vabsduh	vabsduh vD, vA, vB	VA-form	VMX (AltiVec)	Computes \|A - B\| for halfwords.
vabsduw	vabsduw vD, vA, vB	VA-form	VMX (AltiVec)	Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register.
vaddcuq	vaddcuq vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and writes the carry-out to another register.
vaddcuw	vaddcuw vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and writes the carry-out to another vector register.
vaddfp	vaddfp vD, vA, vB	VA-form	VMX (AltiVec)	Adds the contents of two vector registers and places the result in another vector register.
vaddsbs	vaddsbs vD, vA, vB	VX-form	VMX (AltiVec)	Adds 16 signed bytes with saturation (-128..127).
vaddshs	vaddshs vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and saturates the result if it overflows.
vaddsws	vaddsws vD, vA, vB	VX-form	VMX (AltiVec)	Adds 4 signed words with saturation.
vaddubm	vaddubm vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes.
vaddubs	vaddubs vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and saturates the result if it overflows.
vaddudm	vaddudm vD, vA, vB	VX-form	VMX (AltiVec)	Adds 2 doublewords modulo 2^64.
vadduhm	vadduhm vD, vA, vB	VX-form	VMX (AltiVec)	Adds 8 halfwords modulo 65536.
vadduhs	vadduhs vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and saturates the result.
vadduqm	vadduqm vD, vA, vB	VA-form	VMX (AltiVec)	Adds the contents of two vector registers and updates the destination register with the result modulo 2^128.
vadduwm	vadduwm vD, vA, vB	VX-form	VMX (AltiVec)	Adds 4 words modulo 2^32.
vadduws	vadduws vD, vA, vB	VX-form	VMX (AltiVec)	Adds the contents of two vector registers and saturates the result if it exceeds 32 bits.
vand	vand vD, vA, vB	VX-form	VMX (AltiVec)	Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.
vandc	vandc vD, vA, vB	VX-form	VMX (AltiVec)	Bitwise AND of vA with the ones' complement of vB (vA & ~vB).
vavgsb	vavgsb vD, vA, vB	VA-form	VMX (AltiVec)	Performs a signed byte-wise average of two vector registers and stores the result in another vector register.
vavgsh	vavgsh vD, vA, vB	VA-form	VMX (AltiVec)	Performs a signed halfword average operation on vector elements.
vavgsw	vavgsw vD, vA, vB	VA-form	VMX (AltiVec)	Performs a vector average of signed words from two source vectors and stores the result in a destination vector.
vavgub	vavgub vD, vA, vB	VA-form	VMX (AltiVec)	Computes (a+b+1)/2 for bytes.
vavguh	vavguh vD, vA, vB	VA-form	VMX (AltiVec)	Computes (a+b+1)/2 for halfwords.
vavguw	vavguw vD, vA, vB	VA-form	VMX (AltiVec)	Computes (a+b+1)/2 for words.
vbcdadd	vbcdadd vD, vA, vB, PS	VX-form	Vector Crypto	Adds two BCD (Binary Coded Decimal) vectors.
vbcdsub	vbcdsub vD, vA, vB, PS	VX-form	Vector Crypto	Subtracts two BCD vectors.
vbpermd	vbpermd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register.
vbpermq	vbpermq VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs a bit permutation on two vector registers and stores the result in another vector register.
vbrd	vbrd vD, vB	VX-form	VMX (AltiVec)	Reverses bytes within each doubleword.
vbrh	vbrh vD, vB	VX-form	VMX (AltiVec)	Reverses bytes within each halfword (Endian Swap).
vbrq	vbrq vD, vB	VX-form	VMX (AltiVec)	Reverses bytes within the entire 128-bit quadword.
vbrw	vbrw vD, vB	VX-form	VMX (AltiVec)	Reverses bytes within each word.
vcfsx	vcfsx vD, vB, UIM	VX-form	VMX (AltiVec)	Converts signed fixed-point values in a vector register to single-precision floating-point values.
vcfuged	vcfuged vD, vA, vB	VX-form	VMX (AltiVec)	Separates bits of source into two groups based on mask (Power10).
vcfux	vcfux vD, vB, UIM	VX-form	VMX (AltiVec)	Converts 4 unsigned 32-bit integers to floats.
vcipher	vcipher vD, vA, vB	VX-form	Vector Crypto	Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).
vcipherlast	vcipherlast vD, vA, vB	VX-form	Vector Crypto	Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.
vclrlb	vclrlb vD, vA, RB	VX-form	VMX (AltiVec)	Clears the leftmost bytes in a vector register based on the value in a general-purpose register.
vclrrb	vclrrb vD, vA, RB	VX-form	VMX (AltiVec)	Clears the N rightmost bytes of a vector.
vclzb	vclzb vD, vB	VX-form	VMX (AltiVec)	Counts the number of leading zero bits in each byte element of a vector register.
vclzd	vclzd vD, vB	VX-form	VMX (AltiVec)	Counts the number of leading zero bits in each doubleword element of a vector register.
vclzdm	vclzdm VRT, VRA, VRB	X-form	VMX (AltiVec)	Counts the number of leading zeros in each doubleword element of a vector, considering a mask.
vclzh	vclzh vD, vB	VX-form	VMX (AltiVec)	Counts leading zeros in each halfword.
vclzlsbb	vclzlsbb RA, vB	VX-form	VMX (AltiVec)	Counts the number of contiguous leading byte elements in VSR[VRB+32] having a zero least-significant bit.
vclzw	vclzw vD, vB	VX-form	VMX (AltiVec)	Counts the number of leading zero bits in each word element of a vector register.
vcmpbfp	vcmpbfp VRT,VRA,VRB vcmpbfp. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two VSRs word element by word and sets the target VSR if Rc=1.
vcmpeqfp	vcmpeqfp VRT,VRA,VRB vcmpeqfp. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares the elements of two vector registers for equality and stores the result in a third vector register.
vcmpequb	vcmpequb VRT,VRA,VRB vcmpequb. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.
vcmpequd	vcmpequd VRT,VRA,VRB vcmpequd. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.
vcmpequh	vcmpequh VRT,VRA,VRB vcmpequh. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.
vcmpequq	vcmpequq VRT,VRA,VRB vcmpequq. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.
vcmpequw	vcmpequw VRT,VRA,VRB vcmpequw. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.
vcmpgefp	vcmpgefp vD, vA, vB	VC-form	VMX (AltiVec)	Compares 4 floats (A >= B).
vcmpgefp.	vcmpgefp. VRT, VRA, VRB	VC-form	Base	Compares the elements of two vector registers and sets the result in a third vector register based on whether each element is greater than or equal to the corresponding element in the other vector.
vcmpgtfp	vcmpgtfp VRT,VRA,VRB vcmpgtfp. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.
vcmpgtsb	vcmpgtsb VRT,VRA,VRB vcmpgtsb. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.
vcmpgtsd	vcmpgtsd VRT,VRA,VRB vcmpgtsd. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two doublewords of signed integers and sets the result vector based on the comparison.
vcmpgtsh	vcmpgtsh VRT,VRA,VRB vcmpgtsh. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.
vcmpgtsq	vcmpgtsq VRT,VRA,VRB vcmpgtsq. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares two signed quadwords and sets the result based on whether the first is greater than the second.
vcmpgtsw	vcmpgtsw VRT,VRA,VRB vcmpgtsw. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.
vcmpgtub	vcmpgtub vD, vA, vB	VC-form	VMX (AltiVec)	Unsigned > comparison for 16 bytes.
vcmpgtud	vcmpgtud vD, vA, vB	VC-form	VMX (AltiVec)	Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.
vcmpgtuh	vcmpgtuh vD, vA, vB	VC-form	VMX (AltiVec)	Unsigned > comparison for 8 halfwords.
vcmpgtuw	vcmpgtuw vD, vA, vB	VC-form	VMX (AltiVec)	Unsigned > comparison for 4 words.
vcmpneb	vcmpneb VRT,VRA,VRB vcmpneb. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.
vcmpneh	vcmpneh VRT,VRA,VRB vcmpneh. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.
vcmpnew	vcmpnew VRT,VRA,VRB vcmpnew. VRT,VRA,VRB	VC-form	VMX (AltiVec)	Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.
vcmpsq	vcmpsq BF,VRA,VRB	VX-form	VMX (AltiVec)	Compares the signed integer values in two vector registers and updates the condition register.
vcntmbb	vcntmbb RT,VRB,MP	VX-form	VMX (AltiVec)	Counts the number of true (or false) mask bits in a VSR and places the count in the leftmost byte of a GPR.
vcntmbw	vcntmbw RT,VRB,MP	VX-form	VMX (AltiVec)	Counts the number of word elements in a vector register that have bit 0 set to a specified value.
vctsxs	vctsxs vD, vB, UIM	VX-form	VMX (AltiVec)	Converts a vector of floating-point values to signed fixed-point integers with rounding towards zero and saturation.
vctuxs	vctuxs vD, vB, UIM	VX-form	VMX (AltiVec)	Converts 4 floats to 4 unsigned 32-bit integers.
vctzb	vctzb vD, vB	VX-form	VMX (AltiVec)	Counts the number of trailing zero bits in each byte element of a vector register.
vctzd	vctzd vD, vB	VX-form	VMX (AltiVec)	Counts the number of consecutive zero bits starting at bit 63 of each doubleword element in VSR[VRB+32] and places the result into VSR[VRT+32].
vctzh	vctzh vD, vB	VX-form	VMX (AltiVec)	Counts trailing zeros in each halfword.
vctzlsbb	vctzlsbb RA, vB	VX-form	VMX (AltiVec)	Counts the number of trailing zero bits in each byte element of a vector.
vctzw	vctzw vD, vB	VX-form	VMX (AltiVec)	Counts the number of trailing zero bits in each word element of a vector register.
vdivesd	vdivesd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs extended signed doubleword division on vector elements.
vdivesq	vdivesq VRT,VRA,VRB	VX-form	VMX (AltiVec)	Divides the contents of two vector registers and updates the destination register with the quotient.
vdivesw	vdivesw VRT,VRA,VRB	VX-form	VMX (AltiVec)	Divides the contents of two vector registers and updates the result in another vector register.
vdivsd	vdivsd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Divides the contents of two vector registers and updates the result in another vector register.
vdivsq	vdivsq VRT,VRA,VRB	VX-form	VMX (AltiVec)	Divides the contents of two vector registers and updates the destination register with the quotient.
vdivsw	vdivsw VRT,VRA,VRB	VX-form	VMX (AltiVec)	Divides the contents of two vector registers and updates the result in another vector register.
veqv	veqv VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs a logical equivalence operation on the contents of two vector registers and stores the result in another vector register.
vexpandbm	vexpandbm vD, vB	VX-form	VMX (AltiVec)	Expands the mask from bit 0 of each byte element in the source VSR to all bits in the corresponding element in the target VSR.
vexpanddm	vexpanddm vD, vB	VX-form	VMX (AltiVec)	Expands bits from a GPR mask into a doubleword-element vector.
vexpandhm	vexpandhm vD, vB	VX-form	VMX (AltiVec)	Expands bits from a GPR mask into a halfword-element vector.
vexpandqm	vexpandqm vD, vB	VX-form	VMX (AltiVec)	Expands bits from a GPR mask into a quadword-element vector.
vexpandwm	vexpandwm vD, vB	VX-form	VMX (AltiVec)	Expands bits from a GPR mask into a word-element vector.
vexptefp	vexptefp VRT, VRB	VX-form	VMX (AltiVec)	Estimates the result of raising 2 to the power of each element in a vector.
vextddvlx	vextddvlx VRT,VRA,VRB,RC	VA-form	VMX (AltiVec)	Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.
vextdubvlx	vextdubvlx VRT,VRA,VRB,RC	VA-form	VMX (AltiVec)	Extracts a double unsigned byte from two vector registers using a left-index specified by a general-purpose register and places it into another vector register.
vextduhvlx	vextduhvlx VRT,VRA,VRB,RC	VA-form	VMX (AltiVec)	Extracts a double unsigned halfword from two vector registers and places it into another vector register based on the index specified in a general-purpose register.
vextduwvlx	vextduwvlx VRT,VRA,VRB,RC	VA-form	VMX (AltiVec)	Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.
vextractbm	vextractbm RA, vB	VX-form	VMX (AltiVec)	Extracts bit 0 of each byte element from a VSR into a GPR.
vextractd	vextractd RA, vB, UIM	VX-form	VMX (AltiVec)	Extracts a doubleword from a vector into a GPR.
vextractdm	vextractdm RA, vB	VX-form	VMX (AltiVec)	Extracts MSB of each doubleword into a GPR mask.
vextracthm	vextracthm RA, vB	VX-form	VMX (AltiVec)	Extracts MSB of each halfword into a GPR mask.
vextractqm	vextractqm RA, vB	VX-form	VMX (AltiVec)	Extracts the least significant bit of a vector register and places it into a general-purpose register.
vextractub	vextractub RA, vB, UIM	VX-form	VMX (AltiVec)	Extracts an unsigned byte from a vector register and places it into the upper byte of another vector register.
vextractuh	vextractuh RA, vB, UIM	VX-form	VMX (AltiVec)	Extracts a halfword from a vector into a GPR.
vextractuw	vextractuw RA, vB, UIM	VX-form	VMX (AltiVec)	Extracts an unsigned word from a vector register and places it into another vector register using an immediate-specified index.
vextractwm	vextractwm RA, vB	VX-form	VMX (AltiVec)	Extracts the least significant bit of each word element from a vector register and places them into a general-purpose register.
vextsb2d	vextsb2d vD, vB	VX-form	VMX (AltiVec)	Sign-extends the byte elements of a vector register to doublewords.
vextsb2w	vextsb2w vD, vB	VX-form	VMX (AltiVec)	Sign-extends each byte in a vector to a word.
vextsh2d	vextsh2d vD, vB	VX-form	VMX (AltiVec)	Extends the sign of each halfword in a vector to doubleword.
vextsh2w	vextsh2w vD, vB	VX-form	VMX (AltiVec)	Sign-extends halfwords to words.
vextsw2d	vextsw2d vD, vB	VX-form	VMX (AltiVec)	Extends the sign of each word in a vector to doubleword.
vextublx	vextublx RT,RA,VRB	VX-form	VMX (AltiVec)	Extracts an unsigned byte from a vector register and places it into a general-purpose register using the left-index specified in another general-purpose register.
vextuhlx	vextuhlx RT,RA,VRB	VX-form	VMX (AltiVec)	Extracts an unsigned halfword from a vector register and places it into a general-purpose register using the left index specified in another general-purpose register.
vextuwlx	vextuwlx RT,RA,VRB	VX-form	VMX (AltiVec)	Extracts an unsigned word from a vector register and places it into a general-purpose register.
vextuwrx	vextuwrx VRT,RA,RB	VX-form	VMX (AltiVec)	Extracts an unsigned word from a vector register and places it into a general-purpose register.
vgbbd	vgbbd vD, vB	VX-form	VMX (AltiVec)	The contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32].
vgnb	vgnb vD, vB, UIM	VX-form	VMX (AltiVec)	Gathers every Nth bit from a vector register and places it into a general-purpose register.
vinsblx	vinsblx VRT,RA,RB	VX-form	VMX (AltiVec)	Inserts a byte from a general-purpose register into a vector register at an index specified by another general-purpose register.
vinsbvlx	vinsbvlx VRT,RA,VRB	VX-form	VMX (AltiVec)	Inserts a byte from one vector register into another based on an index specified in a general-purpose register.
vinsdlx	vinsdlx VRT,RA,RB	VX-form	VMX (AltiVec)	Inserts a doubleword from a general-purpose register into a vector register at a position specified by another general-purpose register.
vinsertb	vinsertb vD, vB, UIM	VX-form	VMX (AltiVec)	Inserts a byte element from one vector register into another at an immediate-specified index.
vinsertd	vinsertd vD, vB, UIM	VX-form	VMX (AltiVec)	Inserts a doubleword from a GPR into a vector.
vinsertd_p	vinsertd vD, RB, UIM	VX-form	VMX (AltiVec)	Inserts doubleword from GPR into Vector.
vinserth	vinserth vD, vB, UIM	VX-form	VMX (AltiVec)	Inserts a halfword from a GPR into a vector.
vinserth_p	vinserth vD, RB, UIM	VX-form	VMX (AltiVec)	Inserts halfword from GPR into Vector.
vinsertw	vinsertw vD, vB, UIM	VX-form	VMX (AltiVec)	Inserts a word element from one vector register into another vector register at an immediate-specified index.
vinsertw_p	vinsertw vD, RB, UIM	VX-form	VMX (AltiVec)	Inserts word from GPR into Vector.
vinshlx	vinshlx VRT,RA,RB	VX-form	VMX (AltiVec)	Inserts the high halfword of a general-purpose register into a vector register at a position specified by another general-purpose register.
vinshvlx	vinshvlx VRT,RA,VRB	VX-form	VMX (AltiVec)	Inserts halfword from a vector register into another vector register at a position specified by a general-purpose register.
vinshvrx	vinshvrx	VX-form	VMX (AltiVec)	Inserts a halfword from a vector register into another vector register at a position specified by a general-purpose register.
vinsw	vinsw VRT,RB,UIM	VX-form	VMX (AltiVec)	Inserts the contents of a word from a general-purpose register into a vector register at an immediate-specified index.
vinswlx	vinswlx VRT,RA,RB	VX-form	VMX (AltiVec)	Inserts the contents of bits 32:63 of a general-purpose register into byte elements of a vector register based on an index specified in another general-purpose register.
vinswvlx	vinswvlx VRT,RA,VRB	VX-form	VMX (AltiVec)	Inserts a word from a vector register into another vector register at a position specified by a general-purpose register.
vlogefp	vlogefp VRT,VRB	VX-form	VMX (AltiVec)	Estimates the base 2 logarithm of single-precision floating-point elements in a vector register.
vmaddfp	vmaddfp VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs a multiply-add operation on vector elements.
vmaxfp	vmaxfp VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs element-wise maximum of two vector registers and stores the result in a third vector register.
vmaxsb	vmaxsb vD, vA, vB	VA-form	VMX (AltiVec)	Performs a signed byte-wise maximum operation on two vector registers and stores the result in another vector register.
vmaxsd	vmaxsd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Compares the signed doublewords of two vector registers and stores the maximum value in a third vector register.
vmaxsh	vmaxsh vD, vA, vB	VA-form	VMX (AltiVec)	Compares the signed halfwords of two vector registers and stores the maximum values in a third vector register.
vmaxsw	vmaxsw vD, vA, vB	VA-form	VMX (AltiVec)	Compares the signed integer values in each word element of two vector registers and stores the larger value into a third vector register.
vmaxub	vmaxub vD, vA, vB	VA-form	VMX (AltiVec)	Selects maximum value per byte (unsigned).
vmaxuh	vmaxuh vD, vA, vB	VA-form	VMX (AltiVec)	Selects maximum value per halfword (unsigned).
vmaxuw	vmaxuw vD, vA, vB	VA-form	VMX (AltiVec)	Selects maximum value per word (unsigned).
vmhaddshs	vmhaddshs VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs a vector multiply-high-add signed halfword operation with saturation.
vminsb	vminsb vD, vA, vB	VA-form	VMX (AltiVec)	Compares the signed byte elements of two vector registers and stores the minimum values in a third vector register.
vminsd	vminsd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Compares the signed doublewords of two vector registers and stores the minimum values in a third vector register.
vminsh	vminsh vD, vA, vB	VA-form	VMX (AltiVec)	Compares the signed halfwords of two vector registers and selects the minimum value for each corresponding pair.
vminsw	vminsw vD, vA, vB	VA-form	VMX (AltiVec)	Compares the signed integer values in each word element of two vector registers and stores the smaller value into a target vector register.
vminub	vminub vD, vA, vB	VA-form	VMX (AltiVec)	Selects minimum value per byte (unsigned).
vminuh	vminuh vD, vA, vB	VA-form	VMX (AltiVec)	Selects minimum value per halfword (unsigned).
vminuw	vminuw vD, vA, vB	VA-form	VMX (AltiVec)	Selects minimum value per word (unsigned).
vmladduhm	vmladduhm VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs a vector multiply-low-add unsigned halfword modulo operation.
vmodsd	vmodsd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs vector modulo signed doubleword operation.
vmodsq	vmodsq VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.
vmodsw	vmodsw VRT,VRA,VRB	VX-form	VMX (AltiVec)	Performs modulo operation on signed integers in vector registers.
vmrgew	vmrgew vD, vA, vB	VX-form	VMX (AltiVec)	Merges even word elements from two vector registers into a third.
vmrghb	vmrghb vD, vA, vB	VX-form	VMX (AltiVec)	Interleaves high-order bytes from two vectors (Permutation).
vmrghh	vmrghh vD, vA, vB	VX-form	VMX (AltiVec)	Merges the high halfwords of two vector registers into a target vector register.
vmrghw	vmrghw vD, vA, vB	VX-form	VMX (AltiVec)	Merges the high words of two vector registers into a target vector register.
vmrglb	vmrglb vD, vA, vB	VX-form	VMX (AltiVec)	Interleaves low-order bytes.
vmrglh	vmrglh vD, vA, vB	VX-form	VMX (AltiVec)	Interleaves low-order halfwords.
vmrglw	vmrglw vD, vA, vB	VX-form	VMX (AltiVec)	Interleaves low-order words.
vmrgow	vmrgow vD, vA, vB	VX-form	VMX (AltiVec)	Merges odd words from two vectors.
vmsumcud	vmsumcud VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs vector multiply-sum and writes the carry-out of the low-order 128 bits to a destination register.
vmsummbm	vmsummbm VRT,VRA,VRB,VRC	X-form	VMX (AltiVec)	Performs a vector multiply-sum operation with mixed byte elements.
vmsumshm	vmsumshm vD, vA, vB, vC	VA-form	VMX (AltiVec)	Multiplies halfwords and sums adjacent results into words.
vmsumshs	vmsumshs vD, vA, vB, vC	VA-form	VMX (AltiVec)	Performs a vector multiply-sum operation on signed halfwords and saturates the result.
vmsumubm	vmsumubm vD, vA, vB, vC	VA-form	VMX (AltiVec)	Multiplies bytes and sums adjacent results into words.
vmsumudm	vmsumudm VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs a horizontal add of the doubleword elements in VSR[VRA+32] using vmsumudm.
vmsumuhs	vmsumuhs VRT,VRA,VRB,VRC	VA-form	VMX (AltiVec)	Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.
vmul10ecuq	vmul10ecuq VX,VA,VB	VX-form	VMX (AltiVec)	Multiplies the unsigned quadword integer in vector register VA by 10, adds the least-significant bit of VB as a carry-in digit, and writes the carry-out of the result to vector register VX.
vmul10euq	vmul10euq VRT,VRA,VRB	VX-form	VMX (AltiVec)	Multiplies the contents of two vector registers by 10 and extends the result.
vmul10uq	vmul10uq VRT,VRA	VX-form	VMX (AltiVec)	Multiplies the contents of a vector register by 10 and places the result in another vector register.
vmulesb	vmulesb vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the even-indexed bytes of two vector registers and stores the results in a destination vector register.
vmulesd	vmulesd VRT,VRA,VRB	VX-form	VMX (AltiVec)	Multiplies the even doublewords of two vector registers and places the result in another vector register.
vmulesh	vmulesh vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.
vmulesw	vmulesw vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies even-indexed signed words from two vector registers and stores the results in a destination vector register.
vmuleub	vmuleub vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies even-indexed bytes of two vector registers and stores the results in a destination vector register.
vmuleud	vmuleud VRT,VRA,VRB	VX-form	VMX (AltiVec)	Multiplies the even doublewords of two vector registers and places the result in another vector register.
vmuleuh	vmuleuh vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.
vmuleuw	vmuleuw vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the even-numbered words of two vector registers and places the results in a destination vector register.
vmulfp	vmulfp vD, vA, vB	VA-form	VMX (AltiVec)	Multiplies four single-precision floats (Classic VMX).
vmulhsd	vmulhsd vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the signed doublewords of two vector registers and stores the high-order 64 bits of each product in a result vector register.
vmulhsw	vmulhsw vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies the signed integer values in each word element of two vector registers and places the high-order 32 bits of the 64-bit product into the corresponding word element of a third vector register.
vmulhud	vmulhud vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies unsigned doublewords, returning the high 64 bits.
vmulhuw	vmulhuw vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies unsigned words, returning the high 32 bits.
vmulld	vmulld VRT,VRA,VRB	VX-form	VMX (AltiVec)	Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.
vmulosb	vmulosb vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies odd signed bytes to halfwords.
vmulosh	vmulosh vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies odd signed halfwords to words.
vmulosw	vmulosw vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies odd words (1,3) to 64-bit signed result.
vmuloub	vmuloub vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies odd unsigned bytes to halfwords.
vmulouh	vmulouh vD, vA, vB	VX-form	VMX (AltiVec)	Multiplies odd unsigned halfwords to words.
vmulouw	vmulouw vD, vA, vB	VA-form	VMX (AltiVec)	Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.
vmuluwm	vmuluwm VRT,VRA,VRB	VX-form	VMX (AltiVec)	Multiplies the contents of two vector registers and places the low-order 32 bits of each product into a target vector register.
vncipher	vncipher vD, vA, vB	VX-form	Vector Crypto	Performs one round of an AES inverse cipher operation on the intermediate state array.
vncipherlast	vncipherlast vD, vA, vB	VX-form	Vector Crypto	Performs the final round of AES decryption.
vnegd	vnegd vD, vB	VX-form	VMX (AltiVec)	Negates each doubleword integer.
vnegw	vnegw vD, vB	VX-form	VMX (AltiVec)	Negates the contents of each word element in a vector register.
vnor	vnor vD, vA, vB	VX-form	VMX (AltiVec)	Performs a logical NOR operation on the contents of two vector registers and stores the result in another vector register.
vor	vor vD, vA, vB	VX-form	VMX (AltiVec)	Bitwise OR of two 128-bit vectors.
vpdepd	vpdepd vD, vA, vB	VX-form	VMX (AltiVec)	Deposits bits from source to target under control of a mask (Power10).
vperm	vperm vD, vA, vB, vC	VA-form	VMX (AltiVec)	The signature AltiVec instruction. Constructs a new vector by selecting bytes from two source vectors based on a permute control vector.
vpermr	vpermr vD, vA, vB, vC	VA-form	VMX (AltiVec)	Bitwise byte shuffle similar to vperm but for little-endian access optimization.
vpermxor	vpermxor vD, vA, vB, vC	VA-form	Vector Crypto	Permutes bytes from vA and vB, then XORs with vC. Used for finite field arithmetic.
vpextd	vpextd vD, vA, vB	VX-form	VMX (AltiVec)	Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.
vpkpx	vpkpx vD, vA, vB	VX-form	VMX (AltiVec)	Packs the contents of two vector registers into a single vector register, with each source word being considered as a 32-bit pixel and each target halfword as a 16-bit pixel.
vpksdss	vpksdss VRT,VRA,VRB	VX-form	VMX (AltiVec)	Packs signed doublewords from two vector registers into a single vector register with signed saturation.
vpkshss	vpkshss vD, vA, vB	VX-form	VMX (AltiVec)	Packs signed halfwords from two vector registers into a single vector register with signed saturation.
vpkswss	vpkswss vD, vA, vB	VX-form	VMX (AltiVec)	Packs signed words from two vector registers into a single vector register with signed saturation.
vpkswus	vpkswus VRT,VSRA,VSRB	VX-form	VMX (AltiVec)	Packs signed words from two source vectors into one destination vector with unsigned saturation.
vpkudum	vpkudum VRT,VRA,VRB	VX-form	VMX (AltiVec)	Packs the upper halves of doublewords from two source vectors into a destination vector.
vpkuhum	vpkuhum vD, vA, vB	VX-form	VMX (AltiVec)	Packs the upper half of each 16-bit element from two vector registers into a single byte in another vector register.
vpkuhus	vpkuhus vD, vA, vB	VX-form	VMX (AltiVec)	Saturates 8 halfwords to 16 unsigned bytes.
vpkuwum	vpkuwum vD, vA, vB	VX-form	VMX (AltiVec)	Packs the upper half of each word from two vector registers into a single vector register using modulo arithmetic.
vpmsumb	vpmsumb vD, vA, vB	VX-form	Vector Crypto	Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.
vpmsumd	vpmsumd vD, vA, vB	VX-form	Vector Crypto	Performs GF(2) polynomial arithmetic on doublewords.
vpmsumh	vpmsumh vD, vA, vB	VX-form	VMX (AltiVec)	Performs GF(2) polynomial arithmetic on halfwords.
vpmsumw	vpmsumw vD, vA, vB	VX-form	Vector Crypto	Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.
vpopcntb	vpopcntb vD, vB	VX-form	VMX (AltiVec)	Counts the number of bits set to 1 in each byte of a vector register.
vpopcntd	vpopcntd vD, vB	VX-form	VMX (AltiVec)	Counts set bits in each doubleword.
vpopcnth	vpopcnth vD, vB	VX-form	VMX (AltiVec)	Counts set bits in each halfword.
vpopcntw	vpopcntw vD, vB	VX-form	VMX (AltiVec)	Counts the number of bits set to 1 in each word element of a vector register.
vprtybd	vprtybd vD, vB	VX-form	VMX (AltiVec)	Computes parity of bytes within doublewords.
vprtybq	vprtybq vD, vB	VX-form	VMX (AltiVec)	Calculates the parity of each byte in a vector register and stores the result in another vector register.
vprtybw	vprtybw vD, vB	VX-form	VMX (AltiVec)	Calculates the parity of each byte in a vector word and stores the result.
vrefp	vrefp VRT,VRB	VX-form	VMX (AltiVec)	Estimates the reciprocal of single-precision floating-point elements in a vector.
vrfim	vrfim vD, vB	VX-form	VMX (AltiVec)	Rounds each element of a vector toward negative infinity.
vrfin	vrfin vD, vB	VX-form	VMX (AltiVec)	Rounds 4 floats to nearest integer.
vrfip	vrfip vD, vB	VX-form	VMX (AltiVec)	Rounds each element of a vector to the nearest integer towards positive infinity.
vrfiz	vrfiz vD, vB	VX-form	VMX (AltiVec)	Rounds 4 floats to integer (trunc).
vrlb	vrlb vD, vA, vB	VX-form	VMX (AltiVec)	Rotates each byte of the source vector left by a specified number of bits.
vrld	vrld vD, vA, vB	VX-form	VMX (AltiVec)	Rotates each doubleword left.
vrldmi	vrldmi VRT,VRA,VRB	VX-form	VMX (AltiVec)	Rotates the contents of a vector register left by a specified number of bits and inserts the result into another vector register under control of a mask.
vrlh	vrlh vD, vA, vB	VX-form	VMX (AltiVec)	Rotates each halfword left.
vrlq	vrlq vD, vA, vB	VX-form	VMX (AltiVec)	Rotates the contents of a vector register left by a specified number of bits.
vrlqnm	vrlqnm VRT,VRA,VRB	VX-form	VMX (AltiVec)	Rotates the contents of a vector register left by a specified number of bits and performs a bitwise AND operation with a mask derived from another vector register.
vrlw	vrlw vD, vA, vB	VX-form	VMX (AltiVec)	Rotates each word element of the source vector left by a specified number of bits.
vrlwmi	vrlwmi VRT,VRA,VRB	VX-form	VMX (AltiVec)	Rotates the contents of each word element in a vector left by a specified number of bits and inserts the result into another vector under control of a mask.
vrlwnm	vrlwnm VRT,VRA,VRB	VX-form	VMX (AltiVec)	Rotates each word element of the source vector left by a specified number of bits and then performs a bitwise AND operation with a mask.
vsbox	vsbox vD, vA	VX-form	Vector Crypto	Performs the SubBytes operation (S-Box lookup) on a vector.
vsel	vsel vD, vA, vB, vC	VA-form	VMX (AltiVec)	Bitwise selection. copies bits from vA if the corresponding bit in vC is 0, or from vB if vC is 1. (Like 'mux').
vshasigmad	vshasigmad vD, vA, ST, SIX	VX-form	Vector Crypto	Performs the SHA-512 σ0, σ1, Σ0, or Σ1 functions on doubleword elements of vector registers.
vshasigmaw	vshasigmaw vD, vA, ST, SIX	VX-form	Vector Crypto	Performs the Sigma0/Sigma1/sigma0/sigma1 functions for SHA-256.
vsl	vsl vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of a vector register left by a specified number of bits.
vslb	vslb vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each byte element of the source vector left by a specified number of bits.
vsldbi	vsldbi VRT,VRA,VRB,SH	VN-form	VMX (AltiVec)	Shifts the contents of two vector registers left by a specified number of bits and places the result into another vector register.
vslh	vslh vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each halfword left.
vslo	vslo vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of a vector register left by a specified number of bytes.
vslq	vslq vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of a vector register left by a specified number of bits.
vslv	vslv VRT,VRA,VRB	VX-form	VMX (AltiVec)	Shifts the contents of vector elements left by a variable amount.
vslw	vslw vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each of the four words in vA left by the number of bits specified in the corresponding word of vB.
vspltb	vspltb vD, vB, UIM	VX-form	VMX (AltiVec)	Splat a byte from one vector element into all elements of another vector.
vsplth	vsplth vD, vB, UIM	VX-form	VMX (AltiVec)	Duplicates a halfword element across the vector.
vspltisb	vspltisb vD, SIM	VX-form	VMX (AltiVec)	Splat an immediate signed byte value into all elements of a vector register.
vspltish	vspltish vD, SIM	VX-form	VMX (AltiVec)	Fills vector with immediate 5-bit signed value.
vspltisw	vspltisw vD, SIM	VX-form	VMX (AltiVec)	Splat a signed immediate value into all elements of a vector register.
vspltw	vspltw vD, vB, UIM	VX-form	VMX (AltiVec)	Copies a single word element from the source vector into all four word elements of the destination.
vsr	vsr vD, vA, vB	VX-form	VMX (AltiVec)	Shifts vector right by octet count in vB.
vsrab	vsrab vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each byte of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.
vsrah	vsrah vD, vA, vB	VX-form	VMX (AltiVec)	Arithmetic right shift of halfwords.
vsraq	vsraq vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of a vector register right algebraically by a specified number of bits.
vsraw	vsraw vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each word element of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.
vsrb	vsrb vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each byte element of the source vector right by a specified number of bits.
vsrh	vsrh vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of each element in a vector right by a specified number of bits.
vsro	vsro vD, vA, vB	VX-form	VMX (AltiVec)	Shifts vector right by byte count.
vsrq	vsrq vD, vA, vB	VX-form	VMX (AltiVec)	Shifts the contents of a vector register right by a specified number of bits.
vsrv	vsrv vTMP1, vSRC, vSHCT1	X-form	VMX (AltiVec)	Shifts each element of the source vector right by a variable amount specified in another vector.
vsrw	vsrw vD, vA, vB	VX-form	VMX (AltiVec)	Shifts each word element of the source vector right by a specified number of bits.
vstribl	vstribl vD, vB	VX-form	VMX (AltiVec)	Stores the leftmost byte of each element in a vector register to memory.
vstribr	vstribr VRT,VRB vstribr. VRT,VRB	VX-form	VMX (AltiVec)	Isolates the rightmost non-zero byte in a vector string and shifts it to the left.
vstrihr	vstrihr VRT,VRB vstrihr. VRT,VRB	VC-form	VMX (AltiVec)	Isolates the rightmost non-zero halfword in a vector string.
vstril	vstril vD, vB	VX-form	VMX (AltiVec)	Isolates the leftmost element that matches the condition.
vstril_p	vstril. vD, vB	VX-form	VMX (AltiVec)	Isolates the leftmost element and updates CR6.
vstrir	vstrir vD, vB	VX-form	VMX (AltiVec)	Isolates the rightmost element that matches the condition.
vstrir_p	vstrir. vD, vB	VX-form	VMX (AltiVec)	Isolates the rightmost element and updates CR6.
vsubcuq	vsubcuq vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers, adds one, and writes the carry-out to another register.
vsubcuw	vsubcuw vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the unsigned integer values in word elements of two vector registers and writes the result to another vector register, along with the carry-out.
vsubfp	vsubfp vD, vA, vB	VA-form	VMX (AltiVec)	Subtracts four single-precision floats (Classic VMX).
vsubsbs	vsubsbs vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts 16 signed bytes with saturation.
vsubshs	vsubshs vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers and saturates the result to halfword elements.
vsubsws	vsubsws vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts 4 signed words with saturation.
vsububm	vsububm vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers and updates the result in another vector register using modulo operation for bytes.
vsububs	vsububs vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers and saturates the result to zero if it underflows.
vsubudm	vsubudm vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers and places the result in a third vector register, modulo operation.
vsubuhm	vsubuhm vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts 8 halfwords modulo 65536.
vsubuhs	vsubuhs vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts 8 unsigned halfwords with saturation.
vsubuqm	vsubuqm vD, vA, vB	VA-form	VMX (AltiVec)	Subtracts the contents of two vector registers and places the result in another vector register, modulo operation.
vsubuwm	vsubuwm vD, vA, vB	VA-form	VMX (AltiVec)	Subtracts the contents of two vector registers and updates the result in another vector register.
vsubuws	vsubuws vD, vA, vB	VX-form	VMX (AltiVec)	Subtracts the contents of two vector registers and saturates the result if it underflows.
vsum2sws	vsum2sws vD, vA, vB	VA-form	VMX (AltiVec)	Adds the contents of two vector registers and updates the saturation flag.
vsum4sbs	vsum4sbs vD, vA, vB	VA-form	VMX (AltiVec)	Adds the contents of four signed byte elements from two vector registers and saturates the result.
vsum4shs	vsum4shs vD, vA, vB	VA-form	VMX (AltiVec)	Sums every 2 halfwords into a word.
vsum4ubs	vsum4ubs vD, vA, vB	VA-form	VMX (AltiVec)	Sums the unsigned byte elements of two vector registers and saturates the result.
vsumsws	vsumsws vD, vA, vB	VA-form	VMX (AltiVec)	Adds the contents of four word elements of one vector register to a single word element of another vector register and saturates the result.
vupkhpx	vupkhpx vD, vB	VX-form	VMX (AltiVec)	Unpacks high 4 pixels to 4 words.
vupkhsb	vupkhsb vD, vB	VX-form	VMX (AltiVec)	Unpacks the high signed byte from each element of a vector register into halfwords of another vector register.
vupkhsh	vupkhsh vD, vB	VX-form	VMX (AltiVec)	Unpacks the high signed halfwords from a vector register into a new vector register.
vupkhsw	vupkhsw VRT,VRB	VX-form	VMX (AltiVec)	Unpacks the high signed words from a vector register into a doubleword format.
vupklpx	vupklpx vD, vB	VX-form	VMX (AltiVec)	Unpacks low 4 pixels to 4 words.
vupklsb	vupklsb vD, vB	VX-form	VMX (AltiVec)	Unpacks low 8 signed bytes to 8 signed halfwords.
vupklsh	vupklsh vD, vB	VX-form	VMX (AltiVec)	Unpacks low 4 signed halfwords to 4 signed words.
vxor	vxor vD, vA, vB	VX-form	VMX (AltiVec)	Bitwise XOR of two 128-bit vectors.
wait	wait WC,PL wait WC wait	X-form	Base	Stops instruction execution and places the processor in a lower power state until an interrupt occurs.
waitimpl	waitimpl	X-form	Base	Waits for a specific implementation event.
waitrsv	waitrsv	X-form	Base	Waits until a reservation is lost (Multithreading sync).
wrtee	wrtee RS	X-form	Embedded	Updates the EE bit of the MSR from a GPR.
wrteei	wrteei E	X-form	Embedded	Updates the EE bit of the MSR from an immediate.
xmsubasp	xmsubasp XT,XA,XB	XX3-form	VSX	Performs a multiply-subtract operation on single-precision floating-point values.
xor	xor RA, RS, RB	X-form	Base	Performs a bitwise Exclusive OR comparison.
xori	xori RA, RS, UI	D-form	Base	Performs a bitwise XOR with a 16-bit unsigned immediate.
xoris	xoris RA, RS, UI	D-form	Base	Performs a bitwise XOR with a 16-bit immediate shifted left by 16 bits.
xsabsdp	xsabsdp XT, XB	XX2-form	VSX	Computes the absolute value of a double-precision floating-point number.
xsabsqp	xsabsqp vD, vB	X-form	VSX	Computes the absolute value of a quad-precision floating-point number.
xsadddp	xsadddp XT, XA, XB	XX3-form	VSX	Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.
xsaddqp	xsaddqp vD, vA, vB	X-form	VSX	Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).
xsaddqpo	xsaddqpo vD, vA, vB	X-form	VSX	Used for Quad-Precision arithmetic on hardware that splits quads.
xsaddsp	xsaddsp XT, XA, XB	XX3-form	VSX	Adds the contents of two single-precision floating-point numbers and places the result in a double-precision format.
xscmpeqdp	xscmpeqdp XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the target vector register based on equality.
xscmpeqqp	xscmpeqqp VRT,VRA,VRB	X-form	VSX	Compares two quad-precision floating-point values and sets the target vector register to all 1s if they are equal, otherwise all 0s.
xscmpexpdp	xscmpexpdp BF, XA, XB	XX3-form	VSX	Compares the exponents of two double-precision floating-point values in VSX registers and updates the condition register.
xscmpexpqp	xscmpexpqp BF, vA, vB	X-form	VSX	Compares the exponents of two quad-precision floating-point values and updates the condition register.
xscmpgedp	xscmpgedp XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the target vector register based on the comparison result.
xscmpgeqp	xscmpgeqp VRT,VRA,VRB	X-form	VSX	Compares two quad-precision floating-point values and sets the target register based on the comparison.
xscmpgtdp	xscmpgtdp XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the target vector register based on the comparison.
xscmpgtqp	xscmpgtqp VRT,VRA,VRB	X-form	VSX	Compares two quad-precision floating-point values and sets the target vector register to all 1s if the first value is greater than the second, otherwise all 0s.
xscmpodp	xscmpodp BF, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the condition register based on the comparison.
xscmpopoqp	xscmpopoqp BF, vA, vB	X-form	VSX	Compares Quad floats (Signaling on NaN).
xscmpoqp	xscmpoqp BF,VRA,VRB	X-form	VSX	Compares two quad-precision floating-point values and updates the condition register.
xscmpudp	xscmpudp BF, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the condition register based on the comparison.
xscmpuqp	xscmpuqp BF, vA, vB	X-form	VSX	Compares two quad-precision floating-point values and updates the condition register.
xscpsgndp	xscpsgndp XT,XA,XB	X-form	VSX	Copies the sign of a double-precision floating-point value from one register to another.
xscpsgnqp	xscpsgnqp vD, vA, vB	X-form	VSX	Copies sign from B to A (128-bit).
xscvdphp	xscvdphp XT, XB	XX2-form	VSX	Converts a double-precision floating-point value to a half-precision floating-point value with rounding.
xscvdpqp	xscvdpqp vD, vB	X-form	VSX	Converts a double-precision floating-point value to a quad-precision floating-point value.
xscvdpsp	xscvdpsp XT, XB	XX2-form	VSX	Converts a double-precision floating-point value in VSR[XB] to single-precision format and places the result into VSR[XT].
xscvdpspn	xscvdpspn XT,XB	XX2-form	VSX	Converts a scalar single-precision floating-point value to vector single-precision format without raising exceptions for inexact results.
xscvdpsxds	xscvdpsxds XT, XB	XX2-form	VSX	Converts a double-precision floating-point value to a signed doubleword integer using round towards zero.
xscvdpsxw	xscvdpsxw XT,XB	X-form	VSX	Converts a double-precision floating-point number to a signed word, rounding towards zero.
xscvdpsxws	xscvdpsxws XT,XB	X-form	VSX	Converts a double-precision floating-point value to a signed word format using round towards zero.
xscvdpuxds	xscvdpuxds XT, XB	XX2-form	VSX	Converts a double-precision floating-point value to an unsigned 64-bit integer using round towards zero.
xscvdpuxws	xscvdpuxws XT,XB	XX2-form	VSX	Converts a double-precision floating-point value to an unsigned 32-bit integer, rounding towards zero.
xscvhpdp	xscvhpdp XT, XB	XX2-form	VSX	Converts a half-precision floating-point value to a double-precision floating-point value.
xscvqpdp	xscvqpdp vD, vB	X-form	VSX	Converts a quad-precision floating-point value to a double-precision floating-point value with round-to-even rounding.
xscvqpsd	xscvqpsd vD, vB	X-form	VSX	Converts 128-bit Float to 64-bit Signed Integer.
xscvqpsdz	xscvqpsdz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to a signed doubleword integer, rounding towards zero.
xscvqpsqz	xscvqpsqz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero.
xscvqpswz	xscvqpswz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to a signed word format.
xscvqpud	xscvqpud vD, vB	X-form	VSX	Converts 128-bit Float to 64-bit Unsigned Integer.
xscvqpudz	xscvqpudz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to an unsigned doubleword integer, rounding towards zero.
xscvqpuqz	xscvqpuqz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to an unsigned quadword integer, rounding towards zero.
xscvqpuwz	xscvqpuwz VRT,VRB	X-form	VSX	Converts a quad-precision floating-point value to an unsigned word format.
xscvsdqp	xscvsdqp vD, vB	X-form	VSX	Converts a signed doubleword integer from VSR[VRB+32] to quad-precision floating-point in VSR[VRT+32].
xscvspdp	xscvspdp XT, XB	XX2-form	VSX	Converts a single-precision floating-point value in VSR[XB] to double-precision format and places the result into VSR[XT].
xscvsqqp	xscvsqqp VRT,VRB	X-form	VSX	Converts a signed quadword integer to a quad-precision floating-point number and rounds it.
xscvsxddp	xscvsxddp XT,RB	X-form	VSX	Converts a signed doubleword integer from VSX register XB to a double-precision floating-point number in VSX register XT, rounding according to the FPSCR.RN setting.
xscvsxdsp	xscvsxdsp XT,XB	XX2-form	VSX	Converts a signed doubleword integer in a VSX register to a single-precision floating-point number and rounds it.
xscvudqp	xscvudqp vD, vB	X-form	VSX	Converts 64-bit Unsigned Integer to 128-bit Float.
xsdivdp	xsdivdp XT,XA,XB	XX3-form	VSX	Divides the double-precision floating-point value in VSR[XA] by the double-precision floating-point value in VSR[XB].
xsdivqp	xsdivqp vD, vA, vB	X-form	VSX	Divides the contents of two quad-precision floating-point registers and places the result in another register.
xsdivqpo	xsdivqpo vD, vA, vB	X-form	VSX	Used for Quad-Precision arithmetic on hardware that splits quads.
xsdivsp	xsdivsp XT, XA, XB	XX3-form	VSX	Divides the contents of two doubleword elements in VSX registers and places the result in a single-precision format.
xsiexpdp	xsiexpdp XT, XA, XB	XX3-form	VSX	Inserts exponent from one double into another.
xsiexpqp	xsiexpqp VRT,VRA,VRB	X-form	VSX	Inserts the exponent from a doubleword element of one vector register into another vector register.
xsmaddadp	xsmaddadp XT,XA,XB	XX3-form	VSX	Performs a double-precision floating-point multiply-add operation.
xsmaddasp	xsmaddasp XT,XA,XB	XX3-form	VSX	Performs a single-precision floating-point multiply-add operation.
xsmaddmsp	xsmaddmsp FRT,FRB,FRC	XX3-form	VSX	Multiplies two single-precision floating-point values and adds a third, storing the result in the target register (Type-M form).
xsmaddqp	xsmaddqp VRT,VRA,VRB	X-form	VSX	Performs a quad-precision floating-point multiply-add operation with rounding to even.
xsmaxcdp	xsmaxcdp XT, XA, XB	XX3-form	VSX	Computes the maximum of two double-precision floating-point values and stores the result in a vector scalar register.
xsmaxcqp	xsmaxcqp vD, vA, vB	X-form	VSX	Compares two quad-precision floating-point values and selects the maximum.
xsmaxdp	xsmaxdp XT, XA, XB	XX3-form	VSX	Compares the doubleword elements of two vector scalar registers and stores the maximum value in another vector scalar register.
xsmaxjdp	xsmaxjdp XT, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and returns the larger one, with specific handling for zero and NaN values.
xsmaxqp	xsmaxqp vD, vA, vB	X-form	VSX	Selects maximum of two Quad floats.
xsmincdp	xsmincdp XT, XA, XB	XX3-form	VSX	Computes the minimum of two double-precision floating-point numbers and handles NaNs according to Type-C rules.
xsmincqp	xsmincqp vD, vA, vB	X-form	VSX	Compares two quad-precision floating-point values and selects the minimum value.
xsmindp	xsmindp XT, XA, XB	XX3-form	VSX	Computes the minimum of two double-precision floating-point values and places the result into a vector scalar register.
xsminjdp	xsminjdp XT, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and selects the minimum value, handling special cases like NaNs and zeros.
xsminqp	xsminqp vD, vA, vB	X-form	VSX	Selects minimum of two Quad floats.
xsmsubadp	xsmsubadp XT,XA,XB	XX3-form	VSX	Performs a double-precision floating-point multiply-subtract operation.
xsmsubasp	xsmsubasp XT,XA,XB	X-form	VSX	Performs a multiply-subtract-add operation on single-precision floating-point values.
xsmsubqp	xsmsubqp VRT,VRA,VRB xsmsubqpo VRT,VRA,VRB	X-form	VSX	Performs a multiply-subtract operation on quad-precision floating-point values.
xsmuldp	xsmuldp XT,XA,XB	XX3-form	VSX	Multiplies two double-precision floating-point numbers and places the result in a vector register.
xsmulqp	xsmulqp vD, vA, vB	X-form	VSX	Multiplies two quad-precision floating-point numbers and rounds the result to odd.
xsmulsp	xsmulsp XT, XA, XB	XX3-form	VSX	Multiplies two single-precision floating-point numbers and stores the result in a doubleword element of a VSX register.
xsnabsdp	xsnabsdp XT,XB	XX2-form	VSX	Computes the negative absolute value of a double-precision floating-point number.
xsnegdp	xsnegdp XT, XB	XX2-form	VSX	Negates the contents of a double-precision floating-point register and stores the result in another register.
xsnegqp	xsnegqp vD, vB	X-form	VSX	Negates a 128-bit Quad float.
xsnmaddadp	xsnmaddadp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-add operation on double-precision floating-point values.
xsnmaddasp	xsnmaddasp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-add operation on single-precision floating-point values.
xsnmaddmdp	xsnmaddmdp VRT, VRA, VRB, VRC	XX3-form	VSX	Computes the negative of the fused multiply-add of the double-precision floating-point operands, storing the result in the target scalar VSX register (Type-M: target register is used as the addend).
xsnmaddqp	xsnmaddqp VRT,VRA,VRB xsnmaddqpo VRT,VRA,VRB	X-form	VSX	Performs a negative multiply-add operation on quad-precision floating-point values.
xsnmsubadp	xsnmsubadp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-subtract operation on double-precision floating-point values.
xsnmsubasp	xsnmsubasp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-subtract operation on single-precision floating-point values.
xsnmsubmsp	xsnmsubmsp	XX3-form	VSX	Performs a scalar negative multiply-subtract operation in single-precision floating-point, storing the result using the Type-M (multiplicand) form where the target register provides one of the multiplicand operands.
xsnmsubqp	xsnmsubqp VRT,VRA,VRB	X-form	VSX	Performs a negative multiply-subtract operation on quad-precision floating-point values.
xsrdpi	xsrdpi VRT, VRA	X-form	VSX	Rounds a double-precision floating-point value to an integer using the specified rounding mode.
xsrdpic	xsrdpic XT,XB	XX2-form	VSX	Rounds a double-precision floating-point value to an integer using the current rounding mode.
xsrdpim	xsrdpim XT,XB	XX2-form	VSX	Rounds a double-precision floating-point value in VSR[XB] towards negative infinity and places the result into VSR[XT].
xsrdpip	xsrdpip XT,XB	XX2-form	VSX	Rounds a double-precision floating-point value towards positive infinity and stores the result in a vector scalar register.
xsrdpiz	xsrdpiz XT,XB	XX2-form	VSX	Rounds a double-precision floating-point value toward zero and places the result into a vector-scalar register.
xsredp	xsredp XT,XB	XX2-form	VSX	Estimates the reciprocal of a double-precision floating-point value.
xsresp	xsresp XT,XB	XX2-form	VSX	Estimates the reciprocal of a single-precision floating-point value.
xsrintqp	xsrintqp vD, vB	X-form	VSX	Rounds Quad float to nearest Integer.
xsrqpi	xsrqpi vD, vB, R	Z23-form	VSX	Rounds a quad-precision floating-point value in VRB to an integer and places the result in VRT.
xsrqpix	xsrqpix vD, vB, R	Z23-form	VSX	Rounds a Quad float to a Quad integer (Exact).
xsrqpxp	xsrqpxp R, VRT, VRB, RMC	Z23-form	VSX	Rounds a quad-precision floating-point value to extended-precision.
xsrsp	xsrsp XT,XB	X-form	VSX	Rounds a double-precision floating-point value in VSR[XB] to single-precision and stores the result in VSR[XT].
xsrsqrtedp	xsrsqrtedp XT,XB	XX2-form	VSX	Estimates the reciprocal square root of a double-precision floating-point value.
xsrsqrtesp	xsrsqrtesp XT,XB	XX2-form	VSX	Estimates the reciprocal square root of a single-precision floating-point value.
xssqrtdp	xssqrtdp XT, XB	XX2-form	VSX	Computes the unbounded-precision square root of a double-precision floating-point value and rounds it to double-precision format.
xssqrtqp	xssqrtqp vD, vB	X-form	VSX	Computes the square root of a quad-precision floating-point value with unbounded significand precision and exponent range.
xssqrtqpo	xssqrtqpo vD, vB	X-form	VSX	Used for Quad-Precision arithmetic on hardware that splits quads.
xssqrtsp	xssqrtsp XT,XB	XX2-form	VSX	Computes the square root of a single-precision floating-point number in VSX.
xssubdp	xssubdp XT,XA,XB	XX3-form	VSX	Subtracts the contents of two double-precision floating-point registers and places the result in another register.
xssubqp	xssubqp VRT,VRA,VRB xssubqpo VRT,VRA,VRB	X-form	VSX	Subtracts the contents of two quad-precision floating-point registers and handles special cases like NaNs.
xssubqpo	xssubqpo vD, vA, vB	X-form	VSX	Used for Quad-Precision arithmetic on hardware that splits quads.
xssubsp	xssubsp XT, XA, XB	XX3-form	VSX	Subtracts the contents of two single-precision floating-point values and places the result in a vector register.
xstdivdp	xstdivdp BF,XA,XB	XX3-form	VSX	Performs a double-precision floating-point division and sets condition flags based on the result.
xstsqrtdp	xstsqrtdp BF,XB	XX2-form	VSX	Tests the double-precision floating-point value in VSR[XB] and sets condition register field BF based on various flags.
xststdcdp	xststdcdp BF, XB, DCM	XX2-form	VSX	Tests the data class of a double-precision floating-point value in VSR[XB] and sets bits in CR field BF and FPCC accordingly.
xststdcqp	xststdcqp BF, vB, DCM	X-form	VSX	Tests the data class of a quad-precision floating-point value and sets condition register bits based on the result.
xststdcsp	xststdcsp BF, vB, DCM	XX2-form	VSX	Tests the data class of a single-precision floating-point value in a VSX register and sets condition bits accordingly.
xsxexpdp	xsxexpdp XT, XB	XX2-form	VSX	Extracts the exponent from a double-precision floating-point value in VSR and places it into GPR.
xsxsigdp	xsxsigdp XT, XB	XX2-form	VSX	Extracts the significand of a double-precision floating-point value from a VSX register and places it into a general-purpose register.
xsxsigqp	xsxsigqp VRT, VRA	X-form	Floating-Point	Extracts the significand of a quad-precision floating-point number.
xvabsdp	xvabsdp XT, XB	XX2-form	VSX	Computes the absolute value of each double-precision floating-point element in a vector.
xvabssp	xvabssp XT, XB	XX2-form	VSX	Computes absolute value for four single-precision floats.
xvadddp	xvadddp XT, XA, XB	XX3-form	VSX	Adds the contents of two double-precision floating-point elements from two vector registers and places the result into a target vector register.
xvaddsp	xvaddsp XT, XA, XB	XX3-form	VSX	Adds the contents of two single-precision floating-point vector registers and places the result in another vector register.
xvbf16ger2	xvbf16ger2 AT, XA, XB	XX3-form	MMA	Performs BFloat16 (Brain Float) matrix multiply accumulate.
xvcmpeqdp	xvcmpeqdp XT,XA,XB xvcmpeqdp. XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values in vector registers and sets the target register based on equality.
xvcmpeqsp	xvcmpeqsp XT,XA,XB xvcmpeqsp. XT,XA,XB	XX3-form	VSX	Compares each single-precision floating-point element of two VSX registers and sets the corresponding element in the target register to all 1s if they are equal, otherwise all 0s.
xvcmpgedp	xvcmpgedp XT,XA,XB xvcmpgedp. XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the target vector register based on the comparison.
xvcmpgesp	xvcmpgesp XT,XA,XB xvcmpgesp. XT,XA,XB	XX3-form	VSX	Compares each element of two single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.
xvcmpgtdp	xvcmpgtdp XT,XA,XB xvcmpgtdp. XT,XA,XB	XX3-form	VSX	Compares two double-precision floating-point values and sets the target vector register based on the comparison.
xvcmpgtsp	xvcmpgtsp XT,XA,XB xvcmpgtsp. XT,XA,XB	XX3-form	VSX	Compares each single-precision floating-point element in two vector registers and sets the corresponding element in a target vector register to all 1s if the first element is greater than the second, otherwise all 0s.
xvcpsgndp	xvcpsgndp XT,XA,XB	XX3-form	VSX	Copies the sign bit from one double-precision vector element to another.
xvcvbf16spn	xvcvbf16spn XT,XB	XX2-form	VSX	Converts a vector of bfloat16 values to single-precision floating-point format.
xvcvdpsp	xvcvdpsp XT, XB	XX2-form	VSX	Converts double-precision floating-point values in a vector to single-precision format.
xvcvdpsxds	xvcvdpsxds XT, XB	XX2-form	VSX	Converts a double-precision floating-point value to a signed doubleword integer, rounding according to the current rounding mode.
xvcvdpsxws	xvcvdpsxws XT,XB	X-form	VSX	Converts double-precision floating-point values in a vector to signed 32-bit integers with rounding towards zero.
xvcvdpuxds	xvcvdpuxds XT, XB	XX2-form	VSX	Converts double-precision floating-point values in a vector to unsigned doublewords using round towards zero.
xvcvdpuxws	xvcvdpuxws XT,XB	XX2-form	VSX	Converts double-precision floating-point values in a vector to unsigned 32-bit integers with rounding towards zero.
xvcvhpsp	xvcvhpsp XT, XB	XX2-form	VSX	Converts half-precision floating-point values in a vector register to single-precision floating-point values.
xvcvspbf16	xvcvspbf16 XT,XB	XX2-form	VSX	Converts single-precision floating-point values in a vector register to bfloat16 format and stores them in another vector register.
xvcvspdp	xvcvspdp XT, XB	XX2-form	VSX	Converts two floats to two doubles.
xvcvsphp	xvcvsphp XT, XB	XX2-form	VSX	Converts each single-precision floating-point value in a vector register to half-precision and stores the result in another vector register.
xvcvspsxds	xvcvspsxds XT, XB	XX2-form	VSX	Converts single-precision floating-point values in a vector to signed doublewords, rounding towards zero.
xvcvspsxws	xvcvspsxws XT,XB	XX2-form	VSX	Converts a vector of single-precision floating-point numbers to signed integers using round towards zero.
xvcvspuxds	xvcvspuxds XT,XB	XX2-form	VSX	Converts a single-precision floating-point value to an unsigned doubleword integer, rounding according to the current rounding mode.
xvcvspuxws	xvcvspuxws XT,XB	XX2-form	VSX	Converts a single-precision floating-point value to an unsigned word using round towards zero.
xvcvsxddp	xvcvsxddp XT,XB	XX2-form	VSX	Converts signed doublewords from a vector register to double-precision floating-point values and rounds them.
xvcvsxdsp	xvcvsxdsp XT,XB	XX2-form	VSX	Converts signed doubleword elements of a vector register to single-precision floating-point and rounds the result.
xvcvsxwdp	xvcvsxwdp XT,XB	XX2-form	VSX	Converts signed word elements from a vector register to double-precision floating-point elements in another vector register.
xvcvsxwsp	xvcvsxwsp XT, XB	XX2-form	VSX	Converts a signed integer in each word of the source vector to single-precision floating-point and rounds it.
xvcvuxddp	xvcvuxddp VRT, VRA, VRB	XX2-form	VSX	Converts an unsigned doubleword vector element to a double-precision floating-point value.
xvcvuxdsp	xvcvuxdsp VS32,VS64	XX2-form	VSX	Converts an unsigned doubleword to a single-precision floating-point value with rounding.
xvcvuxwsp	xvcvuxwsp XT, XB	XX2-form	VSX	Converts four 32-bit unsigned integers to four floats.
xvdivdp	xvdivdp XT, XA, XB	XX3-form	VSX	Divides the contents of two vector registers and places the result in another vector register.
xvdivsp	xvdivsp XT, XA, XB	XX3-form	VSX	Divides the contents of two vector registers and places the result in another vector register.
xvf16ger2	xvf16ger2 AT, XA, XB	XX3-form	MMA	Performs a vector floating-point general element-wise rank-2 update operation.
xvf16ger2pn	xvf16ger2pn	XX3-form	MMA	Performs a rank-2 update of an accumulator register using 16-bit floating-point outer product, with positive multiply and negative accumulate.
xvf32ger	xvf32ger AT, XA, XB	XX3-form	MMA	Performs a vector floating-point general element-wise reduction with rank-1 update.
xvf64ger	xvf64ger AT, XA, XB	XX3-form	MMA	Performs a vector floating-point general element-wise reduction on 64-bit elements.
xvf64gernn	xvf64gernn	XX3-form	MMA	Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.
xvi16ger2	xvi16ger2 AT, XA, XB	XX3-form	MMA	Performs a rank-2 update of the contents of two registers and updates the condition register.
xvi16ger2s	xvi16ger2s AT, XA, XB	XX3-form	MMA	Performs a vectorized signed integer multiply and accumulate operation with saturation.
xvi4ger8	xvi4ger8 AT, XA, XB	XX3-form	MMA	Performs an accumulation of eight outer products (rank 8 update) using signed 4-bit integers from two vector scalar registers.
xvi4ger8pp	xvi4ger8pp AT, XA, XB	XX3-form	MMA	Unsigned 4-bit integer matrix multiply accumulate.
xvi8ger4	xvi8ger4 AT, XA, XB	XX3-form	MMA	Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.
xvi8ger4pp	xvi8ger4pp AT, XA, XB	XX3-form	MMA	Signed/Unsigned variations of 8-bit matrix multiply accumulate.
xvi8ger4spp	xvi8ger4spp AT,XA,XB	XX3-form	VSX	Performs a vector-scalar operation on 8-bit signed and unsigned integers with saturation.
xviexpdp	xviexpdp XT,XA,XB	XX3-form	VSX	Inserts the exponent from one vector register into another for double-precision floating-point numbers.
xvmaddadp	xvmaddadp XT, XA, XB	XX3-form	VSX	Performs a double-precision floating-point multiply-add operation on vector elements.
xvmaddasp	xvmaddasp XT,XA,XB	XX3-form	VSX	Performs a single-precision floating-point multiply-add operation on vector elements.
xvmaxdp	xvmaxdp XT, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and selects the maximum value for each element.
xvmaxsp	xvmaxsp XT, XA, XB	XX3-form	VSX	Computes the maximum of corresponding single-precision floating-point elements in two vector registers and stores the result in a third vector register.
xvmindp	xvmindp XT, XA, XB	XX3-form	VSX	Compares two double-precision floating-point values and selects the minimum value for each element.
xvminsp	xvminsp XT, XA, XB	XX3-form	VSX	Performs a minimum operation on single-precision floating-point values from two vector scalar registers and stores the result in another vector scalar register.
xvmsubadp	xvmsubadp XT,XA,XB	XX3-form	VSX	Performs a double-precision floating-point multiply-subtract operation on vector elements.
xvmsubasp	xvmsubasp XT,XA,XB	XX3-form	VSX	Performs a vector multiply-subtract operation on single-precision floating-point values.
xvmsubmdp	xvmsubmdp VRT, VRA, VRB, VRC	XX3-form	VSX	Multiplies corresponding double-precision floating-point elements of two VSX registers, subtracts the corresponding element of a third register, and stores the results, using the Type-M (multiplicand) form.
xvmuldp	xvmuldp XT, XA, XB	XX3-form	VSX	Multiplies two double-precision floating-point numbers in vector registers and stores the result.
xvmulsp	xvmulsp XT, XA, XB	XX3-form	VSX	Multiplies the contents of two single-precision floating-point values and places the result into a vector register.
xvnabsdp	xvnabsdp XT,XB	XX2-form	VSX	Computes the negative absolute value of each double-precision floating-point element in a vector.
xvnegdp	xvnegdp XT, XB	XX2-form	VSX	Negates the contents of a double-precision floating-point vector register and stores the result in another vector register.
xvnegsp	xvnegsp XT, XB	XX2-form	VSX	Negates the contents of a single-precision floating-point register.
xvnmaddadp	xvnmaddadp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-add operation on double-precision floating-point elements.
xvnmaddasp	xvnmaddasp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-add operation on single-precision floating-point elements.
xvnmaddmsp	N/A	XX3-form	VSX	Performs a vector single-precision floating-point negative multiply-add operation (Type-M), computing the negation of (XB * XT + XA) for each single-precision element.
xvnmsubadp	xvnmsubadp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-subtract operation on double-precision floating-point elements.
xvnmsubasp	xvnmsubasp XT,XA,XB	XX3-form	VSX	Performs a negative multiply-subtract operation on single-precision floating-point elements.
xvnmsubmdp	xvnmsubmdp VRT, VRA, VRB, VRC	XX3-form	VSX	Performs a negative multiply-subtract operation on double-precision floating-point values.
xvrdpi	xvrdpi XT,XB	XX2-form	VSX	Rounds each element of a double-precision floating-point vector to the nearest integer away from zero.
xvrdpic	xvrdpic XT,XB	XX2-form	VSX	Rounds each double-precision floating-point element of a vector to an integer using the current rounding mode.
xvrdpim	xvrdpim XT,XB	XX2-form	VSX	Rounds the contents of a vector register towards negative infinity and stores the result in another vector register.
xvrdpiz	xvrdpiz XT,XB	XX2-form	VSX	Rounds each double-precision floating-point element in a vector towards zero and stores the result as an integer.
xvredp	xvredp XT,XB	XX2-form	VSX	A double-precision floating-point estimate of the reciprocal of src is placed into doubleword element i of VSR[XT] in double-precision format.
xvresp	xvresp XT,XB	XX2-form	VSX	Estimates the reciprocal of single-precision floating-point values in a vector.
xvrspi	xvrspi XT,XB	XX2-form	VSX	Rounds each element of a vector from single-precision floating-point format to an integer using round to Nearest Away.
xvrspic	xvrspic XT,XB	XX2-form	VSX	Rounds each single-precision floating-point element of a vector to an integer using the current rounding mode.
xvrspim	xvrspim XT,XB	XX2-form	VSX	Rounds each element of a vector from single-precision floating-point format to integer format, rounding towards negative infinity.
xvrspiz	xvrspiz XT,XB	XX2-form	VSX	Rounds each single-precision floating-point element of a vector towards zero and stores the result in another vector.
xvrsqrtedp	xvrsqrtedp XT,XB	XX2-form	VSX	Estimates the reciprocal square root of double-precision floating-point values in vector registers.
xvrsqrtesp	xvrsqrtesp XT,XB	XX2-form	VSX	Estimates the reciprocal square root of single-precision floating-point values in a vector.
xvsqrtdp	xvsqrtdp XT, XB	XX2-form	VSX	Computes the square root of each double-precision floating-point element in a vector.
xvsqrtsp	xvsqrtsp XT, XB	XX2-form	VSX	Computes the square root of each single-precision floating-point element in a vector.
xvsubdp	xvsubdp XT, XA, XB	XX3-form	VSX	Subtracts the contents of two vector registers and places the result in a target vector register.
xvsubsp	xvsubsp XT, XA, XB	XX3-form	VSX	Subtracts the contents of two vector registers and places the result in another vector register.
xvtdivdp	xvtdivdp BF,XA,XB	XX3-form	VSX	Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.
xvtdivsp	xvtdivsp BF,XA,XB	XX3-form	VSX	Performs a vectorized single-precision floating-point division test.
xvtlsbb	xvtlsbb BF,XB	XX2-form	VSX	Tests the least-significant bit of each byte in a VSX vector register and sets a condition register field based on the results.
xvtsqrtdp	xvtsqrtdp BF,XB	XX2-form	VSX	Tests the double-precision floating-point operands in VSR[XB] and sets condition register field BF based on certain conditions.
xvtsqrtsp	xvtsqrtsp BF,XB	XX2-form	VSX	Tests each element of a vector for conditions related to square root operations.
xvtstdcdp	xvtstdcdp XT,XB,DCMX	XX2-form	VSX	Tests each double-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector to either all ones or all zeros based on the match.
xvtstdcsp	xvtstdcsp XT,XB,DCMX	XX2-form	VSX	Tests each single-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector based on the match.
xvxexpdp	xvxexpdp XT,XB	XX2-form	VSX	Extracts the exponent from each double-precision floating-point value in a vector and places it into another vector.
xvxsigdp	xvxsigdp XT,XB	XX2-form	VSX	Extracts the significand of double-precision floating-point values from a vector register and places them into another vector register.
xxblendvb	xxblendvb XT, XA, XB, XC	XX4-form	VSX	Selects bytes from XA or XB based on the MSB of bytes in XC.
xxblendvd	xxblendvd XT, XA, XB, XC	XX4-form	VSX	Selects doublewords from XA or XB based on the MSB of doublewords in XC.
xxblendvh	xxblendvh XT, XA, XB, XC	XX4-form	VSX	Selects halfwords from XA or XB based on the MSB of halfwords in XC.
xxblendvw	xxblendvw XT, XA, XB, XC	XX4-form	VSX	Selects words from XA or XB based on the MSB of words in XC.
xxbrd	xxbrd XT,XB	XX-form	VSX	Reverses the bytes of each doubleword element in a vector register.
xxbrh	xxbrh XT,XB	XX2-form	VSX	Reverses the bytes of each halfword in a vector register.
xxbrw	xxbrw XT,XB	XX2-form	VSX	Reverses the bytes of each word in a vector register.
xxeval	xxeval XT, XA, XB, XC, IMM	8RR:XX4-form	VSX	Performs an arbitrary 3-input boolean logic function (LUT3) on vectors. The 8-bit immediate 'IMM' defines the truth table.
xxextractuw	xxextractuw RT, XS, UIM	XX2-form	VSX	Extracts an unsigned word from a vector register and places it into another vector register.
xxgenpcvbm	xxgenpcvbm XT, XB, IMM	XX2-form	VSX	Generates a permute control vector based on the byte mask in VSR[VRB+32].
xxgenpcvdm	xxgenpcvdm XT, XB, IMM	XX2-form	VSX	Generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT].
xxgenpcvhm	xxgenpcvhm XT, XB, IMM	XX2-form	VSX	Generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32].
xxgenpcvwm	xxgenpcvwm XT, XB, IMM	XX2-form	VSX	Generates a permute control vector (PCV) based on the word mask in VSR[VRB+32] and stores it in VSR[XT].
xxinsertw	xxinsertw XT, RB, UIM	XX2-form	VSX	Inserts a 32-bit word from a GPR into a specific element of a VSR.
xxland	xxland XT, XA, XB	XX3-form	VSX	Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.
xxlandc	xxlandc XT, XA, XB	XX3-form	VSX	vD = vA & ~vB
xxleqv	xxleqv XT, XA, XB	XX3-form	VSX	vD = ~(vA ^ vB) (XNOR)
xxlnand	xxlnand XT, XA, XB	XX3-form	VSX	vD = ~(vA & vB)
xxlnor	xxlnor XT, XA, XB	XX3-form	VSX	Performs a logical NOR operation on the contents of two VSX registers and stores the result in another VSX register.
xxlor	xxlor XT, XA, XB	XX3-form	VSX	Bitwise OR.
xxlorc	xxlorc XT, XA, XB	XX3-form	VSX	vD = vA \| ~vB
xxlxor	xxlxor XT, XA, XB	XX3-form	VSX	Bitwise XOR.
xxmfacc	xxmfacc AT	X-form	MMA	Copies data from an Accumulator back to 4 adjacent VSRs.
xxmrghd	xxmrghd XT, XA, XB	XX3-form	VSX	Merges high doublewords from XA and XB.
xxmrghw	xxmrghw XT, XA, XB	XX3-form	VSX	Merges the high words of two VSX registers into a target VSX register.
xxmrgld	xxmrgld XT, XA, XB	XX3-form	VSX	Merges low doublewords from XA and XB.
xxmrglw	xxmrglw XT, XA, XB	XX3-form	VSX	Merges low words from two VSRs.
xxmtacc	xxmtacc AT	X-form	MMA	Copies data from 4 adjacent VSRs into an Accumulator.
xxperm	xxperm XT, XA, XB, XC	XX4-form	VSX	Performs a vector permute operation on the contents of three VSX registers.
xxpermdi	xxpermdi XT, XA, XB, DM	XX3-form	VSX	Selects two doublewords from the four available in source registers XA and XB based on a 2-bit selector.
xxpermr	xxpermr XT, XA, XB, XC	XX4-form	VSX	Little-endian optimized permute.
xxpermx	xxpermx XT, XA, XB, XC, UIM	XX4-form	VSX	Permutes bytes from two source vectors using a control vector and a 3-bit selector.
xxsel	xxsel XT, XA, XB, XC	XX4-form	VSX	Selects elements from two source vectors based on a mask vector.
xxsetaccz	xxsetaccz AT	X-form	MMA	Clears a 512-bit Accumulator register (composed of 4 VSRs) to zero.
xxsldwi	xxsldwi XT,XA,XB,SHW	XX3-form	VSX	Shifts the contents of two vector registers left by a specified number of words and places the result into another vector register.
xxsplti32dx	xxsplti32dx XT, IX, IMM	8RR:D-form	VSX	Splats a 32-bit immediate into a doubleword index.
xxspltib	xxspltib XT, IMM	X-form	VSX	Copies an immediate byte value into each byte element of a vector register.
xxspltidp	xxspltidp XT, IMM	8RR:D-form	VSX	Spatially duplicates a 32-bit immediate (converted to double) into both double elements.
xxspltiw	xxspltiw XT, IMM	8RR:D-form	VSX	Spatially duplicates a 32-bit immediate into all 4 words of the target.
xxspltw	xxspltw XT, XS, UIM	XX2-form	VSX	Replicates a word element from one vector register into all elements of another vector register.
xxswapd	xxswapd XT, XB	XX2-form	VSX	Swaps the two doublewords in the register.
xxvger4spp	N/A	XX3-form	MMA	Performs a rank-4 update of an accumulator using 8-bit signed/unsigned integer GER operations with saturation, accumulating only positive multiply results into positive accumulate positions.