fdivs

Floating Point Divide Single Precision

fdivs FRT,FRA,FRB

Divides the contents of two single precision floating point registers.

Details

For fdivs, the value in register FRB is divided by the value in register FRA, and the result is placed into register FRT.

Pseudocode Operation

FRT <- (FRA) / (FRB)

Programming Note

The fdivs instruction performs a single-precision floating-point division. Ensure that neither operand is zero to avoid division by zero exceptions. The FPSCR register may be updated with status flags such as overflow or underflow. This operation can raise exceptions if the result overflows, underflows, or is invalid (e.g., NaN).

Example

fdivs f1, f2, f3

Encoding

Binary Layout
18
0
LI
6
AA
30
LK
31
 
Format XO-form
Opcode 0xEC000024
Extension Floating-Point
Registers Altered FPSCR

Operands

  • FRT
    Target Floating Point Register
  • FRA
    Source Floating Point Register
  • FRB
    Source Floating Point Register