pmxvf64gernp

Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

pmxvf64gernp AT,XAp,XB,XMSK,YMSK

Performs a masked vector floating-point operation with negative multiplication and positive accumulation.

Details

The pmxvf64gernp instruction performs a masked vector floating-point operation with negative multiplication and positive accumulation.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

if 'xvf64ger' | 'xvf64gerpp' | 'xvf64gerpn' | 'xvf64gernp' | 'xvf64gernn' then do
    XMSK ←0b1111
    YMSK ←0b11
end
vsrc1.qword[0] ←VSR[32×AX+Ap]
vsrc1.qword[1] ←VSR[32×AX+Ap+1]
vsrc2        ←VSR[32×BX+B]
do i = 0 to 3
do j = 0 to 1
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then do
        reset_flags()

        src1 ←bfp_CONVERT_FROM_BFP64(vsrc1.dword[i])
        src2 ←bfp_CONVERT_FROM_BFP64(vsrc2.dword[j])
        acc  ←bfp_CONVERT_FROM_BFP64(ACC[AT][i].dword[j])

        if 'pmxvf64ger'   then v ←bfp_MULTIPLY( src1, src2 )
        if 'pmxvf64gerpp' then v ←bfp_MULTIPLY_ADD( src1, src2, acc )
        if 'pmxvf64gerpn' then v ←bfp_MULTIPLY_ADD( src1, src2, bfp_NEGATE(acc) )
        if 'pmxvf64gernp' then v ←bfp_MULTIPLY_ADD( src1, src2, bfp_NEGATE(acc) )
        if 'pmxvf64gernn' then v ←bfp_MULTIPLY_ADD( src1, src2, acc )

        r ←bfp_ROUND_TO_BFP64_DEFAULT(FPSCR.RN,v)

        if 'pmxvf64gernp' then r ←bfp_NEGATE(r)
        if 'pmxvf64gernn' then r ←bfp_NEGATE(r)

        ACC[AT][i].dword[j] ←bfp64_CONVERT_FROM_BFP(r)

        if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
        if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
        if vxisi_flag=1 then SetFX(FPSCR.VXISI)
        if ox_flag=1 then SetFX(FPSCR.OX)
        if ux_flag=1 then SetFX(FPSCR.UX)
        if xx_flag=1 then SetFX(FPSCR.XX)
    end
    else
        ACC[AT][i].dword[j] ←0x0000_0000_0000_0000
end
end

Programming Note

This instruction is used for performing masked vector floating-point operations with negative multiplication and positive accumulation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. The operation involves converting BFP64 values, performing arithmetic operations, rounding, and handling exceptions based on flags set during computation.

Example

pmxvf64gernp acc0, vs2, vs3, 15, 15

Encoding

Binary Layout

XAp

XMSK

YMSK

Format MMIRR:XX3-form

Opcode

Extension VSX

Registers Altered FPSCR, VXSNAN, VXIMZ, VXISI, OX, UX, XX

Operands

AT
Target Vector Register
XAp
Index for Source Vector Register 1
XB
Index for Source Vector Register 2
XMSK
Mask for Source Vector Register 1
YMSK
Mask for Source Vector Register 2