pmxvf64gernp

Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

pmxvf64gernp AT,XAp,XB,XMSK,YMSK

Performs a masked vector floating-point operation with negative multiplication and positive accumulation.

Encoding

Binary Layout

0:5

XAp

6:11

12:17

18:23

XMSK

24:29

YMSK

30:63

Format MMIRR:XX3-form

Opcode 0x07900000EC0003D0

Extension VSX

Operands

AT
Target Vector Register
XAp
Index for Source Vector Register 1
XB
Index for Source Vector Register 2
XMSK
Mask for Source Vector Register 1
YMSK
Mask for Source Vector Register 2

Example

pmxvf64gernp acc0, vs2, vs3, 15, 15

Registers Altered

FPSCR, VXSNAN, VXIMZ, VXISI, OX, UX, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a masked 2×2 generalized outer product (rank-1 update GER) on 64-bit floating-point elements, using negative multiplication and positive accumulation ('np' suffix). The XMSK and YMSK operands control participation of rows and columns respectively. This is a prefixed VSX instruction requiring VSX and prefix support.

Operation

acc ← AT
for i in 0 to 1 do
  if XMSK[i] = 1 then
    for j in 0 to 1 do
      if YMSK[j] = 1 then
        a ← XAp[i*64:(i+1)*64-1]
        b ← XB[j*64:(j+1)*64-1]
        prod ← -1.0 × a × b
        acc[i*64+j*64:(i*64+j*64+63)] ← acc[i*64+j*64:(i*64+j*64+63)] + prod
      end if
    end for
  end if
end for
AT ← acc

Programming Note

This instruction is used for performing masked vector floating-point operations with negative multiplication and positive accumulation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. The operation involves converting BFP64 values, performing arithmetic operations, rounding, and handling exceptions based on flags set during computation.