xvi4ger8pp

VSX Vector Integer 4-bit GER (Rank-8 Update) Plus/Plus

xvi4ger8pp AT, XA, XB

Unsigned 4-bit integer matrix multiply accumulate.

Details

The xvi4ger8pp instruction performs a vector integer 4-bit GER (Rank-8 Update) operation on the VSX registers, multiplying corresponding elements of two matrices and accumulating the results into an accumulator register. It uses masks to selectively process elements and saturates the results if they exceed the 32-bit signed integer range.

Pseudocode Operation

For each integer value i from 0 to 7 and each integer value j from 0 to 7, do the following.
    If bit i of XMSK is equal to 1 and bit j of YMSK is equal to 1, do the following.
        Let prod be the product of the 4-bit signed integer value in element i of VSR[XA] and the 4-bit signed integer value in element j of VSR[XB].
        Let result be the sum of prod to the 32-bit signed integer value in element j of ACC[AT][i].
        If result is less than −231, result saturates to −231 and SAT is set to 1.
        If result is greater than 231 −1, result saturates to 231 −1 and SAT is set to 1.
        result is placed into element j of ACC[AT][i] in 32-bit signed integer format.
    Otherwise, ACC[AT][i][j] is set to 0x0000_0000.

Programming Note

This instruction is commonly used for matrix multiplication and accumulation operations on VSX registers with saturation handling. Ensure that the input matrices are correctly aligned and masked as per requirements. The instruction operates at a privilege level that allows access to FPSCR and XER, and it may raise exceptions if there are issues with operand alignment or access rights. Performance can be optimized by ensuring that the masks (XMSK and YMSK) are efficiently set to minimize unnecessary computations.

Example

xvi4ger8pp acc0, vs2, vs3

Encoding

Binary Layout
60
0
AT
6
XA
11
XB
16
35
21
 
Format XX3-form
Opcode 0xF0000023
Extension MMA
Registers Altered FPSCR, XER

Operands

  • AT
    Accumulator
  • XA
    Src A
  • XB
    Src B