xvi4ger8pp

VSX Vector Integer 4-bit GER (Rank-8 Update) Plus/Plus

xvi4ger8pp AT, XA, XB

Unsigned 4-bit integer matrix multiply accumulate.

Encoding

Binary Layout

60

0:5

AT

6:10

XA

11:15

XB

16:20

35

21:31

 

Format XX3-form

Opcode 0xEC000110

Extension MMA

Operands

• AT
  Accumulator
• XA
  Src A
• XB
  Src B

Example

xvi4ger8pp acc0, vs2, vs3

Registers Altered

FPSCR, XER

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs an unsigned 4-bit integer matrix multiplication with rank-8 accumulation, accumulating the result with plus-signed saturation. This MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, treating both input and output as unsigned values. The plus/plus variant saturates on overflow using unsigned saturation semantics.

Operation

AT ← ACC[AT] + (XA × XB)

Programming Note

This instruction is commonly used for matrix multiplication and accumulation operations on VSX registers with saturation handling. Ensure that the input matrices are correctly aligned and masked as per requirements. The instruction operates at a privilege level that allows access to FPSCR and XER, and it may raise exceptions if there are issues with operand alignment or access rights. Performance can be optimized by ensuring that the masks (XMSK and YMSK) are efficiently set to minimize unnecessary computations.