vsum2sws

Vector Sum-across Partial (1/2) Signed Word Saturate

vsum2sws vD, vA, vB

Adds the contents of two vector registers and updates the saturation flag.

Details

The vsum2sws instruction adds the signed integer values in word elements 0 and 1 of VSR[VRA+32] to the signed integer value in word element 1 of VSR[VRB+32], and places the low-order 32 bits of the result into word element 1 of VSR[VRT+32]. It also adds the signed integer values in word elements 2 and 3 of VSR[VRA+32] to the signed integer value in word element 3 of VSR[VRB+32], and places the low-order 32 bits of the result into word element 3 of VSR[VRT+32]. If any intermediate result saturates, the saturation flag (SAT) is set.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    temp ←EXTS(VSR[VRB+32].dword[i].word[1])
    do j = 0 to 1
        temp ←temp + EXTS(VSR[VRA+32].dword[i].word[j])
    end
    VSR[VRT+32].dword[i].word[0] ←0x0000_0000
    VSR[VRT+32].dword[i].word[1] ←si32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end
VSR[VRT+32].word[0] ←0x0000_0000
VSR[VRT+32].word[2] ←0x0000_0000

Programming Note

This instruction is useful for performing saturated addition of word elements in vector registers. Ensure that the VSCR.SAT flag is checked after execution to handle saturation cases. The instruction operates on 32-bit signed integers and requires the vector facility to be enabled (MSR.VEC=1).

Example

vsum2sws vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1672
 
Format VA-form
Opcode 0x10000688
Extension VMX (AltiVec)
Registers Altered VSCR.SAT

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Accumulator
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register