vsum2sws

Vector Sum-across Partial (1/2) Signed Word Saturate

vsum2sws vD, vA, vB

Adds the contents of two vector registers and updates the saturation flag.

Details

Sums pairs of signed word elements from vA and accumulates into doublewords conceptually, storing the lower 32 bits of saturated results in alternating word positions of vD. The instruction sets the saturation bit (VSCR[SAT]) if any result overflows a signed 32-bit word. This is a Classic VMX (AltiVec) instruction.

Pseudocode Operation

for i in 0 to 1 do
  sum ← sign_extend_64(vA[i*2]) + sign_extend_64(vA[i*2+1]) + sign_extend_64(vB[i*2])
  vD[i*2] ← SATURATE_SIGNED_WORD(sum)
  if overflow then VSCR[SAT] ← 1
endfor

Programming Note

This instruction is useful for performing saturated addition of word elements in vector registers. Ensure that the VSCR.SAT flag is checked after execution to handle saturation cases. The instruction operates on 32-bit signed integers and requires the vector facility to be enabled (MSR.VEC=1).

Example

vsum2sws vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1672
 
Format VA-form
Opcode 0x10000688
Extension VMX (AltiVec)
Registers Altered VSCR.SAT

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Accumulator
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register