vrld

Vector Rotate Left Doubleword

vrld vD, vA, vB

Rotates each doubleword left.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

196

21:31

 

Format VX-form

Opcode 0x100000C4

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Data
• vB
  Rotate Count

Example

vrld vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rotates each of the two 64-bit elements in vA left by the number of bits specified by the corresponding 64-bit element in vB. The rotate count is masked to bits 0-5 (modulo 64). No condition register or status flags are affected.

Operation

for i in 0 to 1 do
  shift_amount ← vB[i*64+0:i*64+63] & 0x3F
  vD[i*64+0:i*64+63] ← ROTL64(vA[i*64+0:i*64+63], shift_amount)

Programming Note

The vrld instruction is commonly used for bit manipulation tasks that require rotating doublewords within a vector. Ensure that the source vectors are properly aligned to avoid unexpected behavior. This instruction operates at user privilege level and will raise an exception if the VEC bit in the MSR register is not set.