vaddfp

Vector Add Floating-Point

vaddfp vD, vA, vB

Adds the contents of two vector registers and places the result in another vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

10

21:31

 

Format VA-form

Opcode 0x1000000A

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vaddfp vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vaddfp, each element of the source vectors VRA and VRB is added to produce corresponding elements in the destination vector VRT.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_ADD(src1,src2)
end

Programming Note

The vaddfp instruction adds corresponding elements of two source vectors and stores the results in a destination vector. Ensure that the Vector Facility is enabled by setting MSR.VEC to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on single-precision floating-point numbers and processes four elements per operation.