mtvsrwm

Move to VSR Word Mask

mtvsrwm VRT,RB

Moves a word mask from a general-purpose register to a vector scalar register.

Encoding

Binary Layout

4

0:5

VRT

6:10

18

11:15

RB

16:20

1602

21:31

 

Format VX-form

Opcode 0x10120642

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Scalar Register
• RB
  Source General Purpose Register

Example

mtvsrwm v1, r5

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bits 60-63 of GPR[RB] are used to set the corresponding word elements in VSR[VRT+32] to either all 0s or all 1s based on the bit value.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    if GPR[RB].bit[60+i]=0 then
        VSR[VRT+32].word[i] ←0x0000_0000
    else
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
end

Programming Note

This instruction is used to set each word in a vector register to either all zeros or all ones based on the corresponding bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction operates on 32-bit words and requires the source general-purpose register to be properly aligned for bit manipulation.