bcdadd.

Binary Coded Decimal Add Record

bcdadd. VRT,RA,RB

Adds two packed decimal integers and updates the condition register.

Encoding

Binary Layout
0
VRT
VRA
VRB
PS
 
Format XO-form
Opcode 0x10000401
Extension Decimal Floating-Point

Operands

  • VRT
    Target Vector Storage Register
  • RA
    Source General Purpose Register containing the first packed decimal integer
  • RB
    Source General Purpose Register containing the second packed decimal integer
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • PS
    Programmable Sign Code
  • vTmp
    Target Vector-Scalar Register
  • vA
    Source Vector-Scalar Register
  • vB
    Source Vector-Scalar Register
  • RT
    Target General Purpose Register

Example

bcdadd. v1, r4, r5

Registers Altered

CR0, XER, FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The bcdadd. instruction adds two binary coded decimal numbers stored in vector registers VRA and VRB, and stores the result in vector register VRT. The PS field specifies whether to set the sign code to 0b1100 or 0b1111 if the unbounded result is zero.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
VRT[32] ← bcd_ADD(VRA[32], VRB[32], PS)
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← ox_flag | inv_flag

Programming Note

When bit 3 of CR field 6 is set to 1 by bcdadd. or bcdsub., either an overflow occurred or one or both operands are not valid encodings of decimal values.