dcffixqq

Double-Precision Floating-Point Fix to Quadword

dcffixqq RT,RA

Converts a double-precision floating-point value to a quadword integer.

Encoding

Binary Layout

18

0:5

LI

6:29

AA

30

LK

31

 

Format X-form

Opcode 0xFC0007C4

Extension Floating-Point

Operands

• RT
  Target General Purpose Register
• RA
  Source General Purpose Register

Example

dcffixqq r3, r4

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a double-precision decimal floating-point value to a 128-bit signed quadword integer, storing the result in a GPR pair or related register file location. This Floating-Point category instruction does not update condition registers but may set exception flags in FPSCR. The conversion uses the current rounding mode from FPSCR.

Operation

RT ← CONVERT_DFP_TO_INT128(FRA, FPSCR[RN])

Programming Note

The dcffixqq instruction is commonly used for converting double-precision floating-point numbers to integers, rounding towards zero. Ensure that the input value in RA is within the range representable by a quadword integer to avoid overflow or underflow exceptions. This instruction operates at user privilege level and does not require any specific ordering or alignment of registers.