drdpq

Decimal Round To DFP Quad-Precision

drdpq FRT, vB

Rounds DFP Quad (128-bit) to DFP Long (64-bit).

Encoding

Binary Layout

63

0:5

FRT

6:10

/

11:15

vB

16:20

770

21:30

/

31

 

Format X-form

Opcode 0xFC000604

Extension Decimal Floating-Point

Operands

• FRT
  Target Long
• vB
  Source Quad

Example

drdpq f1, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Round a DFP quad (128-bit) value from VSR vB to DFP long (64-bit) precision using the rounding mode in FPSCR[RN], and store the result in FPR FRT. This is a Decimal Floating-Point (DFP) instruction. FPSCR status fields are updated to reflect rounding or conversion results.

Operation

long_value ← round_dfp_quad_to_long(vB, FPSCR[RN])
FRT ← long_value
FPSCR[...] ← updated as per rounding

Programming Note

The drdpq instruction is used for rounding decimal floating-point numbers to quad-precision. Ensure that the input number in FRA[p] is within the valid range for quad-precision format to avoid overflow or underflow exceptions. The rounding mode is controlled by the FPSCR register, so make sure it's set according to your application's requirements before executing drdpq.